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ZL50063GAC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
ZL50063 Data Sheet
22
Zarlink Semiconductor Inc.
Figure 10 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 32Mbps
4.0 Port High-Impedance Control
The input pins, LORS and BORS, select whether the Local (LSTo0-15) and Backplane (BSTo0-15) output streams,
respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active
LOW).
Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-15/BSTo0-15, to transmit bi-state
channel data.
Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-15/BSTo0-15, of the device to
invoke a high impedance output on a per-channel basis. The Local/Backplane Output Enable Bit (LE/BE) of the
Local/Backplane Connection Memory has direct per-channel control on the high impedance state of the
Local/Backplane output streams, L/BSTo0-15. Programming a LOW state in the connection memory LE/BE bit will
set the stream output of the device to high impedance for the duration of the channel period. See “Local Connection
Memory Bit Definition,” on page 30 and “Backplane Connection Memory Bit Definition,” on page 31 for
programming details.
The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET
operation,
e.g. following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a
particular system application, although it may be driven under logic control if preferred.
The Local/Backplane output enable control in order of highest priority is: RESET
, ODE, OSB, LE/BE.
RESET
(input pin)
ODE
(input pin)
OSB
(Control
Register bit)
LE/BE
(Local /
Backplane
Connection
Memory bit)
LORS/BORS
(input pin)
LSTo0-15/
BSTo0-15
0XXX0HIGH
0XXX1HI-Z
10XX0HIGH
10XX1HI-Z
110X0HIGH
Table 1 - Local and Backplane Output Enable Control Priority
Bit Advancement, -1
Bit Advancement, -2
Bit Advancement, -3
FP8o
System Clock
BSTo/LSTo0-15
Bit Advancement = 0
BSTo/LSTo0-15
Bit Advancement = -1
(Default)
Bit Advancement = -3
BSTo/LSTo0-15
Bit Advancement = -2
BSTo/LSTo0-15
131.072 MHz
Ch255
Ch255
Ch255
Ch255
Ch0
Ch0
Ch0
Ch0
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
Bit 1
Bit 0 Bit 7 Bit 6 Bit 5
Bit 1
Bit 0 Bit 7 Bit 6 Bit 5
Bit 4
Bit 4
Bit Advancement, 0
ZL50063 Data Sheet
23
Zarlink Semiconductor Inc.
5.0 Data Delay Through the Switching Paths
Serial data which goes into the device is converted into parallel format and written to consecutive locations in the
data memory. Each data memory location corresponds to the input stream and channel number. Channels written
to any of the buffers during Frame N will be read out during Frame N+2. The input bit delay and output bit
advancement have no impact on the overall data throughput delay.
In the following paragraphs, the data throughput delay (T) is represented as a function of ST-BUS frames, input
channel number, (m), and output channel number (n). For 32.768Mbps data rate, there are 512 channels on each
stream. The input channel number (m) and output channel number (n) can therefore have a range of 0 to 511. The
data throughput delay under various input channel and output channel conditions can be summarized as:
T = 2 frames + (n - m)
The data throughput delay (T) is: T = 2 frames + (n - m). Assuming that m (input channel) and n (output channel)
are equal, we have the figure below, in which the delay between the input data being written and the output data
being read is exactly 2 frames.
Figure 11 - Data Throughput Delay with Input Ch0 Switched to Output Ch0
110X1HI-Z
11100HIGH
11101HI-Z
1111XACTIVE
(HIGH or LOW)
RESET
(input pin)
ODE
(input pin)
OSB
(Control
Register bit)
LE/BE
(Local /
Backplane
Connection
Memory bit)
LORS/BORS
(input pin)
LSTo0-15/
BSTo0-15
Table 1 - Local and Backplane Output Enable Control Priority (continued)
Frame
Frame N
Frame N+1 Frame N+2 Frame N+3 Frame N+4 Frame N+5
Frame N Data Frame N+1Data Frame N+2 Data Frame N+3 Data Frame N+4 Data Frame N+5 Data
Serial Input Data
Serial Output Data
Frame N-2 Data Frame N-1 Data Frame N Data Frame N+1 Data Frame N+2 Data Frame N+3 Data
2 Frames + 0
ZL50063 Data Sheet
24
Zarlink Semiconductor Inc.
Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay
time between the input channel being written and the output channel being read exceeds 2 frames.
Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch13
Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time
between the input channel being written and the output channel being read is less than 2 frames.
Figure 13 - Data Throughput Delay with Input Ch13 Switched to Output Ch0
6.0 Microprocessor Port
The 16K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port
consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS
, DS, R/W
and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories,
and the Local Connection and Data Memories. Each memory has 8,192 locations. See Table 5, Address Map for
Data and Connection Memory Locations (A14 = 1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the switch not receiving a master clock, the microprocessor port shall
complete the DTA
handshake when accessed, but any data read from the bus will be invalid.
7.0 Device Power-up, Initialization and Reset
7.1 Power-Up Sequence
The recommended power-up sequence is for the V
DD_IO
supply (nominally +3.3V) to be established before the
power-up of the V
DD_PLL
and V
DD_CORE
supplies (nominally +1.8V). The V
DD_PLL
and V
DD_CORE
supplies may be
powered up simultaneously, but neither should 'lead' the V
DD_IO
supply by more than 0.3V.
All supplies may be powered-down simultaneously.
Frame
Frame N
Frame N+1 Frame N+2 Frame N+3 Frame N+4 Frame N+5
Frame N Data Frame N+1Data Frame N+2 Data Frame N+3 Data Frame N+4 Data Frame N+5 Data
Serial Input Data
Serial Output Data
Frame N-2 Data Frame N-1 Data Frame N Data Frame N+1 Data Frame N+2 Data Frame N+3 Data
2 Frames + (n - m)
Frame
Frame N
Frame N+1 Frame N+2 Frame N+3 Frame N+4 Frame N+5
Frame N Data Frame N+1Data Frame N+2 Data Frame N+3 Data Frame N+4 Data Frame N+5 Data
Serial Input Data
Serial Output Data
Frame N-2 Data Frame N-1 Data Frame N Data Frame N+1 Data Frame N+2 Data Frame N+3 Data
2 Frames + (n - m)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

ZL50063GAC

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Buy ZL50063GAC
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs
Lifecycle:
New from this manufacturer.
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