ZL50063 Data Sheet
58
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Figure 24 - JTAG Test Port Timing Diagram
AC Electrical Characteristics
- JTAG Test Port Timing
Characteristic Sym Min Typ Max Units Notes
1 TCK Clock Period t
TCKP
100 ns
2 TCK Clock Pulse Width High t
TCKH
80 ns
3 TCK Clock Pulse Width Low t
TCKL
80 ns
4 TMS Set-up Time t
TMSS
10 ns
5 TMS Hold Time t
TMSH
10 ns
6 TDi Input Set-up Time t
TDIS
20 ns
7 TDi Input Hold Time t
TDIH
60 ns
8 TDo Output Delay t
TDOD
30 ns C
L
=30pF
9TRST
pulse width t
TRSTW
200 ns
t
TMSH
t
TMSS
t
TCKL
t
TCKH
t
TCKP
t
TDIS
t
TDIH
t
TDOD
t
TRSTW
TMS
TCK
TDi
TDo
TRST
c Zarlink Semiconductor 2003 All rights reserved.
APPRD.
ISSUE
DATE
ACN
Package Code
Previous package codes:
Conforms to JEDEC MS - 034
Except dimensions 'A1' and 'b'.
2 LAYERS (4 LAYERS)
1. Controlling dimensions are in MM.
2. Seating plane is defined by the spherical crown of
3. Not to scale.
4. Ball arrangement: 14 x 14 array
the solder balls.
NOTES:-
A2
TOP VIEW
J
BOTTOM VIEW
SIDE VIEW
I
J
b
N
e
E
E1
I
D
D1
DIMENSION
A
A1
0.850.75
0.600.40
1.0 REF.
1.00 BSC
196
15.00 BSC
15.00 BSC
1.0 REF.
12.95
12.95
13.70
13.70
MIN
1.35 (1.55)
0.30
MAX
0.50
1.75 (1.97)
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2
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2
C Patent rights to use these components in and I
2
C System, provided that the system
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2
C Standard Specification as defined by Philips.
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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ZL50063GAC

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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