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ZL50063GAC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
ZL50063 Data Sheet
28
Zarlink Semiconductor Inc.
• Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in
Section 10.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
DD_IO
when not driven from an external source.
• Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is
set to a high impedance state.
• Test Reset (TRST
)
TRST
provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when
not driven from an external source. This pin MUST be pulled low
for normal operation.
10.2 TAP Registers
The ZL50063 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an
Instruction Register and three Test Data Registers.
10.2.1 Test Instruction Register
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to
define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please
refer to Figure 24 for JTAG test port timing.
10.2.2 Test Data Registers
10.2.2.1 The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the ZL50063 core logic.
10.2.2.2 The Bypass Register
The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.
10.2.2.3 The Device Identification Register
The JTAG device ID for the ZL50063 is 0C38F14B
H
.
Version, Bits <31:28>:0000
Part No., Bits <27:12>:1100 0011 1000 1111
Manufacturer ID, Bits <11:1>:0001 0100 101
Header, Bit <0> (LSB):1
10.3 Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
ZL50063 Data Sheet
29
Zarlink Semiconductor Inc.
11.0 Memory Address Mappings
When the most significant bit, A14, of the address bus is set to ’1’, the microprocessor performs an access to one of
the device’s internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local
Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location
within the particular memory is being accessed.
Table 5 - Address Map for Data and Connection Memory Locations (A14 = 1)
The device contains two data memory blocks, one for received Backplane data and one for received Local data. For
all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored
sequentially in the relevant data memory.
11.1 Local Data Memory Bit Definition
The 8-bit Local Data Memory (LDM) has 8,192 positions. The locations are associated with the Local input streams
and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the addresses
of the streams and the channels. The LDM is read-only and configured as follows:
Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
Address Bit Description
A14 Selects memory or register access (0 = register, 1 = memory).
Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane
Data) is accessed depends on the MS[2:0] bits in the Control Register.
A13-A9 Stream address (0 - 15)
Streams 0 to 15 are used
A8-A0 Channel address (0 - 511)
Channels 0 to 511 are used when serial stream is at 32.768Mbps
Bit Name Description
15:8 Reserved Set to a default value of 8’h00.
7:0 LDM Local Data Memory - Local Input Channel Data.
The LDM[7:0] bits contain the timeslot data from the Local side input TDM
stream. LDM[7] corresponds to the first bit received, i.e. bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 6, ST-BUS and GCI-Bus Input Timing
Diagram for the arrival order of the bits.
Table 6 - Local Data Memory (LDM) Bits
ZL50063 Data Sheet
30
Zarlink Semiconductor Inc.
11.2 Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 8,192 positions. The locations are associated with the Backplane
input streams and channels. As explained previously, address bits A13-A0 of the microprocessor define the
addresses of the streams and the channels. The BDM is read-only and configured as follows:
Note that the Backplane Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
11.3 Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 8,192 addresses of 16-bit words. Each address, accessed through bits
A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition
for each 16-bit word is presented in Table 8 for Source-to-Local connections.
The most-significant bit in the memory location, LSRC, selects the switch configuration for Backplane-to-Local or
Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the
LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-15) in place of data defined by the
Source Control, Stream and Channel Address bits.
Bit Name Description
15:8 Reserved Set to a default value of 8’h00.
7:0 BDM Backplane Data Memory - Backplane Input Channel Data.
The BDM[7:0] bits contain the timeslot data from the Backplane side input TDM
stream. BDM[7] corresponds to the first bit received, i.e. bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 6, ST-BUS and GCI-Bus Input Timing
Diagram for the arrival order of the bits.
Table 7 - Backplane Data Memory (BDM) Bits
Bit Name Description
15 LSRC Local Source Control Bit
When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.
14 LMM Local Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Local or Backplane Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Local Connection Memory).
13 LE Local Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the LORS pin.
When HIGH, the channel is active.
12:9 LSAB[3:0] Source Stream Address Bits
The binary value of these 4 bits represents the input stream number.
Ignored when LMM is set HIGH.
Table 8 - LCM Bits for Source-to-Local Switching
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

ZL50063GAC

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Digital Bus Switch ICs
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