ZL50063GAC Datasheet ZL50063GAC | P25-P27

ZL50063 Data Sheet

Zarlink Semiconductor Inc.

7.2 Initialization

Upon power up, the device should be initialized by applying the following sequence:

7.3 Reset

The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is

then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and

BORS, the output streams LSTo0-15 and BSTo0-15 are set to HIGH or high impedance, and all internal registers

and counters are reset to the default state.

The RESET

pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A

delay of an additional 250µs must also be waited before the first microprocessor access is performed following

the de-assertion of the RESET

pin; this delay is required for determination of the frame pulse format.

In addition, the reset signal must be de-asserted less than 12µs after the frame boundary or more than 13µs after

the frame boundary, as illustrated in Figure 14. This can be achieved, for example, by synchronizing the

de-assertion of the reset signal with the input frame pulse FP8i

Figure 14 - Hardware RESET

De-assertion

1 Ensure the TRST

pin is permanently LOW to disable the JTAG TAP controller.

2Set ODE pin to LOW. This sets the LSTo0-15 outputs to HIGH or high impedance, dependent on the

LORS input value, and sets the BSTo0-15 outputs to HIGH or high impedance, dependent on BORS

input value. Refer to Pin Description for details of the LORS and BORS pins.

3 Reset the device by asserting the RESET

pin to zero for at least two cycles of the input clock, C8i. A

delay of an additional 250µs must also be applied before the first microprocessor access is

performed following the de-assertion of the RESET

pin; this delay is required for determination of the

input frame pulse format.

4 Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer

to Section 8.3, Connection Memory Block Programming.

5Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will

not occur at the serial stream outputs.

FP8i

RESET

12µs

13µs

De-assertion of RESET

must not fall within this window

RESET

assertion

RESET de-assertion

RESET

(case 1)

(case 2)

ZL50063 Data Sheet

Zarlink Semiconductor Inc.

8.0 Connection Memory

The device includes two connection memories, the Local Connection Memory and the Backplane Connection

Memory.

8.1 Local Connection Memory

The Local Connection Memory (LCM) is a 16-bit wide memory with 8,192 memory locations to support the Local

output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane

(LSRC = LOW) or the Local (LSRC = HIGH) port and determines the Backplane-to-Local or Local-to-Local data

routing. Bits[14:13] select the control modes of the Local output streams, the per-channel Message Mode and the

per-channel high impedance output control modes. In Connection Mode (bit[14] = LOW), bits[12:0] select the

source stream and channel number as detailed in Table 2. In Message Mode (bit[14] = HIGH), bits[12:8] are unused

and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that

the output channel is not tri-stated.

8.2 Backplane Connection Memory

The Backplane Connection Memory (BCM) is a 16-bit wide memory with 8,192 memory locations to support the

Backplane output port. The most significant bit of each word, bit[15], selects the source stream from either the

Backplane (BSRC = HIGH) or the Local (BSRC = LOW) port and determines the Local-to-Backplane or

Backplane-to-Backplane data routing. Bit[14:13] select the control modes of the Backplane output streams, namely

the per-channel Message Mode and the per-channel high impedance output control mode. In Connection Mode

(bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 2. In Message Mode

(bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be

HIGH for Message Mode to ensure that the output channel is not tri-stated.

The Control Register bits MS[2:0] must be set to 000 to select the Local Connection Memory for the write and read

operations via the microprocessor port. The Control Register bits MS[2:0] must be set to 001 to select the

Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 6.0,

Microprocessor Port, and Section 13.1, Control Register (CR) for details on microprocessor port access.

8.3 Connection Memory Block Programming

This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after

power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming

8.3.1 Memory Block Programming Procedure:

• Set the MBP bit in the Control Register from LOW to HIGH.

•Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,

LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection

Memory. The remaining bit positions are loaded with zeros as shown in Table 3.

Source Stream Bit Rate Source Stream No. Source Channel No.

32Mbps Bits[12:9]

legal values 0:15

Bits[8:0]

legal values 0:511

Table 2 - Local and Backplane Connection Memory Configuration

ZL50063 Data Sheet

Zarlink Semiconductor Inc.

Table 3 - Local Connection Memory in Block Programming Mode

The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into

bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as

shown in Table 4.

Table 4 - Backplane Connection Memory in Block Programming Mode

The Block Programming Register bit, BPE will be automatically reset LOW within 125µs, to indicate completion of

memory programming.

The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the

Block Programming Register or the MBP bit of the Control Register.

Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a

device reset, can be used.

During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS

pins, irrespective of the values in bits[14:13] of the connection memory.

9.0 Memory Built-In-Self-Test (BIST) Mode

As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is

placed “out-of-service” or isolated from live traffic.

The memory BIST mode is enabled through the microprocessor port (Section 13.7, Memory BIST Register).

Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The

memory test result is monitored through the Memory BIST Register.

10.0 JTAG Port

The ZL50063 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit

shall be controlled by an external Test Access Port (TAP) Controller.

10.1 Test Access Port (TAP)

The Test Access Port (TAP) consists of four input pins and one output pin described as follows:

• Test Clock Input (TCK)

TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the

shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in

Boundary-Scan Mode.

• Test Mode Select Input (TMS)

The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS

signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V

DD_IO

when not

driven from an external source.

15 14 13 1211109876543210

LBPD2LBPD1LBPD00000000000000

15 14 13 1211109876543210

BBPD2BBPD1 BBPD0 0000000000000

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ZL50063GAC

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