CDP68HC68T1M Datasheet CDP68HC68T1MZ, CDP68HC68T1EZ, CDP68HC68T1M2Z | P13-P15

FN1547.9

Decemember 8, 2015

Watchdog

If this bit is set high, the watchdog circuit has detected a

CPU failure.

Test Mode

When this bit is set high, the device is in the TEST MODE.

First-time Up

Power-on reset sets this bit high. This signifies that data in

the RAM and Clock is not valid and should be initialized.

Interrupt True

A high in this bit signifies that one of the three interrupts

(Power Sense, Alarm, and Clock) is valid.

Power-sense Interrupt

This bit set high signifies that the power-sense circuit has

generated an interrupt.

Alarm Interrupt

When the seconds, minutes and hours time and alarm

counter are equal, this bit will be set high. Status Register

must be read before loading Interrupt Control Register for

valid alarm indication after alarm activates.

Clock Interrupt

A periodic interrupt will set this bit high.

All bits are reset by a power-on reset except the “FIRST-

TIME UP” which is set. All bits except the power-sense bit

are reset after a read of this register.

Pin Signal Description

SCK (Serial Clock Input) (Note 13)

This input causes serial data to be latched from the MOSI

input and shifted out on the MISO output.

MOSI (Master Out/Slave In) (Note 13)

Data bytes are shifted in at this pin, most significant bit

(MSB) first.

MISO (Master In/Slave Out)

Data bytes are shifted out at this pin, most significant bit

(MSB) first.

CE (Chip Enable) (Note 14)

A positive chip-enable input. A low level at this input holds

the serial interface logic in a reset state, and disables the

output driver at the MISO pin.

NOTES:

13. These inputs will retain their previous state if the line driving them

goes into a High-Z state.

14. The CE input has as internal pull-down device, if the input is in a

low state before going to High Z, the input can be left in a High Z.

STATUS REGISTER (Read Only) - Address 30H

D7 D6 D5 D4 D3 D2 D1 D0

0 WATCHDOG TEST

MODE

FIRST

TIME

INTERRUPT

TRUE

POWER

SENSE

INTERRUPT

ALARM

INTERRUPT

CLOCK

INTERRUPT

TRUTH TABLE

MODE

SIGNAL

CE SCK (Note 11) MOSI MISO

DISABLE

RESET

L INPUT DISABLED INPUT DISABLED HIGH Z

WRITE H CPOL = 1

CPOL = 0

DATA BIT LATCH HIGH Z

READ H CPOL = 1

CPOL = 0

X NEXT DATA BIT

SHIFTED OUT

(Note 12)

NOTES:

11. When interfacing to CDP68HC05 microcontrollers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer’s Control Register.

12. MISO remains at a high Z until 8-bits of data are ready to be shifted out during a READ. It remains at a high Z during the entire WRITE cycle.

CDP68HC68T1

FN1547.9

Decemember 8, 2015

Functional Description

The Serial Peripheral Interface (SPI) utilized by the

CDP68HC68T1 is a serial synchronous bus for address and

data transfers. The clock, which is generated by the

microcomputer is active only during address and data

transfers. In systems using the CDP68HC05C4 or

CDP68HC05D2, the inactive clock polarity is determined by

the CPOL bit in the microcomputer’s Control Register. A

unique feature of the CDP68HC68T1 is that it automatically

determines the level of the inactive clock by sampling SCK

when CE becomes active (see Figure 8). Input data (MOSI)

is latched internally on the internal strobe edge and output

data (MISO) is shifted out on the shift edge, as defined by

Figure 8. There is one clock for each data bit transferred

(address, as well as data bits are transferred in groups of 8).

Address and Data Format

There are three types of serial transfer:

1. Address Control - Figure 9.

2. READ or WRITE Data - Figure 10.

3. Watchdog Reset (actually a non-transfer) Figure 11.

The Address/Control and Data bytes are shifted MSB first,

Into the serial data input (MOSI) and out of the serial data

output (MISO).

Any transfer of data requires an Address/Control byte to

specify a Write or Read operation and to select a Clock or

RAM location, followed by one or more bytes of data.

Data is transferred out of MISO for a Read and into MOSI for

a Write operation.

Address/Control Byte - (see Figure 9)

It is always the first byte received after CE goes true. To

transmit a new address, CE must first go false and then true

again. Bit 5 is used to select between Clock and RAM

locations.

SHIFT

INTERNAL

STROBE

INTERNAL

STROBE

SHIFT

SCK

CPOL = 1

SCK

CPOL = 0

MOSI MSB MSB -1

NOTE: “CPOL” is a bit that is set in the microcomputer’s Control

FIGURE 8. SERIAL RAM CLOCK (SCK) AS A FUNCTION OF

MCU CLOCK POLARITY (CPOL)

BIT 7 6 5 4 3 2 1 0

W/R

0 CLK RAM A4 A3 A2 A1 A0

04 A0 through A4 Selects 5-bit HEX Address of RAM or specifies Clock Register. Most Significant Address

Bit. If equal to “1”, A0 through A4 selects a Clock Register. If equal to “0”, A0 through A4

selects one of 32 RAM locations. Must be set to ”0” when not in Test Mode 7W/R W/R = “1”

initiates one or more WRITE cycles.W/R = “0”, initiates one or more READ cycles.

5CLK RAM

7W/R

NOTE: SCK can be either polarity.

FIGURE 9. ADDRESS/CONTROL BYTE-TRANSFER WAVEFORMS

A1 A0A3A4

CLOCK

0W/R

MOSI

RAM

SCK (NOTE)

CDP68HC68T1

FN1547.9

Decemember 8, 2015

Read/Write Data (See Figure 10)

Read/Write data follows the Address/Control byte.

Watchdog Reset (See Figure 11)

When watchdog operation is selected, CE must be toggled

periodically or a CPU reset will be outputted.

Address and Data

Data transfers can occur one byte at a time (Figure 12) or in

a multibyte burst mode (Figure 13). After the Real-Time

Clock enabled, an Address/Control word is sent to set the

CLOCK or RAM and select the type of operation (i.e., Read

or Write). For a single-byte Read or Write, one byte is

transferred to or from the Clock Register or RAM location

specified in the Address/Control byte and the Real-Time

Clock is then disabled. Write cycle causes the latched Clock

Incrementing continues after each transfer until the device is

disabled. After incrementing to 1FH the address will “wrap”

to 00H and continue. Therefore, when the RAM is selected

the address will “wrap” to 00H and when the clock is

selected the address will “wrap” 20H.

D7 D6 D5 D4 D3 D2 D1 D0

7 6543210BIT

D1 D0D3D4D5D6D7

SCK (NOTE)

MOSI

MISO

NOTE: SCK can be either polarity.

FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS

SERVICE

TIME

SERVICE

TIME

SCK

CPUR

FIGURE 11. WATCHDOG OPERATION WAVEFORMS

CDP68HC68T1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

CDP68HC68T1M

Mfr. #:

Buy CDP68HC68T1M

Manufacturer:

Renesas / Intersil

Description:

Real Time Clock PERIPH SPIAL-TIME- CLK 20W IND

Lifecycle:

New from this manufacturer.

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CDP68HC68T1M

CDP68HC68T1M

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