19
FN1547.9
Decemember 8, 2015
FIGURE 18. EXAMPLE OF A SYSTEM WITH A BATTERY BACKUP
System Diagrams (Continued)
AC
LINE
REGULATOR
POR V
DD
V
SYS
V
BATT
PSE
CPUR
INT
CLK
XTAL
LINE
OUT
CE
SPI
V
SS
20k
1k
0.047
V
DD
RTC
22M
R
CHARGE
0.1
100k
V
DD
3
NC
V
DD
RESET
CDP68HC05C4B
IRQ
OSC1
PORT
SPI
V
SS
(EPS)
ENABLED
POWER
SUPPLY
CDP68HC68T1
20
FN1547.9
Decemember 8, 2015
Example of an automotive system. The V
SYS
and LINE inputs can be used to sense the ignition turning on and off. An
external switch is included to activate the system without turning on the ignition. Also, the CMOS CPU is not powered down
with the system V
DD
, but is held in a low power reset mode during power down. When restoring power the CDP68HC68T1
will enable the CLK OUT pin and set the PSE and CPUR
high.
Important Application Note: Those units with a code of 6PG have delayed alarm interrupts of 8.3ms regardless of
CDP68HC68T1’s operating frequency. (See "Functional Description", INT on page 10.) In addition, reading the Status
Register before delayed alarm activates will disable alarm signal.
FIGURE 19. AUTOMOTIVE SYSTEM DIAGRAM
System Diagrams (Continued)
XTAL
LINE V
DD
V
SYS
V
BATT
POR
2MHz
PSE
CPUR
CLK OUT
SPI
CE
INT
T1
V
SS
V
DD
RESET
OSC1
IRQ
SPI
PORT
CDP68HC05C4B
V
SS
PORT
5V
REG
+
-
12V
IGNITION
3
CLOCK BUTTON
ENABLED POWER
CDP68HC68T1
21
FN1547.9
Decemember 8, 2015
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask
.
Reliability reports are also available from our website at www.intersil.com/support
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
December 8, 2015 FN1547.9 Updated Ordering Information Table on page 2.
Page 3: Changed Theta JA values and added Theta JC values:
16ld PDIP Theta Ja from 90 to 85. Theta Jc 35 (Notes 1,3)
16ld SOIC Theta Ja from 100 to 65. Theta Jc 26 (Notes 2,3)
20ld SOIC Theta Ja from 95 to 60. Theta Jc 26 (Notes 2,3)
Added Notes 2 and 3
Updated Pb-free Reflow Profile link
Added Revision History and About Intersil sections.
Updated POD M20.3 to latest revision. Changes:
Top View:
Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion)
Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion)
Side View:
Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion)
Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion)
Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994"
Updated to new POD format by moving dimensions from table onto drawing and adding land pattern
CDP68HC68T1

CDP68HC68T1M

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock PERIPH SPIAL-TIME- CLK 20W IND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union