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9P936AGLF

P1-P3P4-P6P7-P9P10-P12
IDT
TM
/ICS
TM
Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
4
Recommended Operating Condition (VDDQ2.5/1.8 = 1.8V +/- 0.1V)
(
see note1
)
T
A
= 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low level input voltage V
IL
BUF_INT, BUF_INC 0.35 x V
DDQ
V
High level input voltage V
IH
BUF_INT, BUF_INC 0.65 x V
DDQ
V
DC input signal voltage
(note 2)
V
IN
-0.3 V
DDQ
+ 0.3 V
DC - BUF_INT, BUF_INC 0.3 V
DDQ
+ 0.4 V
AC - BUF_INT, BUF_INC 0.6 V
DDQ
+ 0.4 V
Output differential cross-
voltage (note 4)
V
OX
V
DDQ
/2 - 0.1 V
DDQ
/2 + 0.1 V
Input differential cross-
voltage (note 4)
V
IX
V
DDQ
/2 - 0.15 V
DDQ
/2 V
DDQ
/2 + 0.15 V
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allow able DC excursion of diff erential input.
4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at w hich the differential signal must be changed.
Differential input signal
voltage (note 3)
V
ID
3. Di
ff
erential inputs signal voltages speci
f
ies the di
ff
erential voltage [VTR-V
C
P] r e q uir ed
f
or sw itching, w here VTR is the true input level and
VCP is the complimentary input level.
SPECIFICATION
IDT
TM
/ICS
TM
Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
5
Timing Requirements VDDQ2.5/1.8 = 1.8 V +/- 0.1V
T
A
= 0 - 70°C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS -40 MAX
UNITS
Max clock frequency freq
op
125 400 MHz
Application Frequency Range freq
A
pp
160 400 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
15 µs
SPECIFICATION
Switching Characteristics (VDDQ2.5/1.8 = 1.8V +/- 0.1V)
(
see note 1
)
T
A
= 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Period jitter T
j
it
(p
er
)
Period jitter -40 40 ps
Half-period jitter T
(j
it_h
p
er
)
Half period jitter -60 60 ps
Cycle to Cycle T
c
c
-T
c
c
Cycle to Cycle jitter -40 40 ps
Dynamic Phase Offset T
(
DPO
)
-50 50 ps
Static Phase Offset T
(
SPO
)
-50 0 50 ps
Output to Output Skew t
skew
DDR(0:5) 40 ps
Output Duty Cycle t
dut
y
47 53 ps
Output clock slew rate t
sl(i)
Measured from 20% to 80% of
VDDQ
1.5 3 V/ns
1. Switching characteristics guaranteed for operating frequency range
SPECIFICATION
IDT
TM
/ICS
TM
Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
6
Electrical Characteristics - Input/Supply/Common Output Parameters (VDDQ2.5/1.8 = 2.5V +/- 0.2V)
T
A
= 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Current I
IH
V
I
= V
DD
or GND -10 µA
Input Low Current I
IL
V
I
= V
DD
or GND 10 µA
I
DDAVDD2.5
R
L
= 120
Ω,
C
L
= 12pf @ 200MHz
20 23 mA
I
DDVDDQ2.5/1.8
R
L
= 120
Ω,
C
L
= 12pf @ 200MHz 220 250 mA
Input Clamp Voltage V
IK
V
DDQ
= 2.5V, Iin = -18mA -1
V
High-level output voltage V
OH
I
OH
= -12 mA 1.7 V
Low-level output voltage V
OL
I
OL
= 12 mA 0.6 V
Input Capacitance C
IN
V
I
= GND or V
DDQ
234pF
Output Capacitance C
OUT
V
OUT
= GND or V
DDQ
234pF
Input clock slew rate t
sl(i)
Input clock 1 2.5 4 V/ns
Operating Supply
Current
SPEC
Recommended Operating Condition (VDDQ2.5/1.8 = 2.5V +/- 0.2V)
(
see note1
)
T
A
= 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low level input voltage V
IL
BUF_INT, BUF_INC V
DDQ
/2 - 0.18 V
High level input voltage V
IH
BUF_INT, BUF_INC V
DDQ
/2 + 0.18 V
DC input signal voltage
(note 2)
V
IN
-0.3 V
DDQ
+ 0.3 V
DC - BUF_INT, BUF_INC 0.36 V
DDQ
+ 0.6 V
AC - BUF_INT, BUF_INC 0.7 V
DDQ
+ 0.6 V
Output differential cross-
voltage (note 4)
V
OX
V
DDQ
/2 - 0.15 V
DDQ
/2 + 0.15 V
Input differential cross-
voltage (note 4)
V
IX
V
DDQ
/2 - 0.2 V
DDQ
/2 V
DDQ
/2 + 0.2 V
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allow able DC excursion of diff erential input.
4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at w hich the differential signal must be changed.
3. Diff erential inputs signal voltages specifies the diff erential voltage [VTR-VCP] required for sw itching, w here VTR is the true input level and
VCP is the complimentary input level.
Differential input signal
voltage (note 3)
V
ID
SPECIFICATION
P1-P3P4-P6P7-P9P10-P12

9P936AGLF

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Clock Buffer PC BUFFER
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