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9P936AGLF

P1-P3P4-P6P7-P9P10-P12
IDT
TM
/ICS
TM
Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
7
Timing Requirements VDDQ2.5/1.8 = 2.5V +/- 0.2V
T
A
= 0 - 70°C Supply Voltage AVDD2.5 = 2.5V+/-0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
Max clock frequency freq
o
p
45 500 MHz
Application Frequency Range freq
A
pp
95 233 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
15 µs
SPECIFICATION
Switching Characteristics (VDDQ2.5/1.8 = 2.5V +/- 0.2V )
(
see note 1
)
T
A
= 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V, VDDQ2.5/1.8 = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Period jitter T
j
it
(p
er
)
Period jitter -60 60 ps
Half-period jitter T
(j
it_h
p
er
)
Half period jitter -75 75 ps
Cycle to Cycle Jitter T
c
c
-T
c
c
Cycle to Cycle jitter -60 60 ps
Static Phase Offset T
(
SPO
)
-50 0 50 ps
Output to Output Skew T
skew
DDR(0:5) 40 ps
Output Duty Cycle t
dut
y
47 53 ps
Output clock slew rate t
sl(o)
Measured from 20% to 80% of
VDDQ
1.5 4 V/ns
1. Switching characteristics guaranteed for operating frequency range
SPECIFICATION
IDT
TM
/ICS
TM
Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
8
1. The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D4
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D5
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
Stop Bit
How to Read:
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4
(H)
• ICS clock will
acknowledge
• Controller (host) sends a dummy command code
• ICS clock will
acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will
acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will
acknowledge
each byte
one at a
time
.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D5
(H)
• ICS clock will
acknowledge
• ICS clock will send the
byte count
• Controller (host) acknowledges
• ICS clock sends first byte
(Byte 0) through byte
7
• Controller (host) will need to acknowledge each
byte
• Controller (host) will send a stop bit
Notes:
IDT
TM
/ICS
TM
Low Skew Dual Bank DDR I/II Fan-out Buffer 1084C 12/03/09
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
9
Note: Bytes not shown are reserved and should not be altered.
I
2
C Table: Output Control Register
Pin # Name Control Function Type 0 1 Default
Bit 7
BUFF_IN_T/C Frequency Detect RW OFF ON 1
Bit 6
FB_OUT_T/C FB_OUT Control RW Disable Enable 1
Bit 5
DDR_T5/C5 Output Control RW Disable Enable 1
Bit 4
DDR_T4/C4 Output Control RW Disable Enable 1
Bit 3
DDR_T3/C3 Output Control RW Disable Enable 1
Bit 2
DDR_T2/C2 Output Control RW Disable Enable 1
Bit 1
DDR_T1/C1 Output Control RW Disable Enable 1
Bit 0
DDR_T0/C0 Output Control RW Disable Enable 1
I
2
C Table: Byte Count Register
Pin # Name Control Function Type 0 1 Default
Bit 7
BC7 RW 0
Bit 6
BC6 RW 0
Bit 5
BC5 RW 0
Bit 4
BC4 RW 0
Bit 3
BC3 RW 1
Bit 2
BC2 RW 1
Bit 1
BC1 RW 1
Bit 0
BC0 RW 1
Pin # Name Control Function Type 0 1 Default
Bit 7
DDR_CSkw3 RW 0000 = 0 1101 = 600 0
Bit 6
DDR_CSkw2 RW 0100 = 150 1110 = 750 0
Bit 5
DDR_CSkw1 RW 1000 = 300 1111 = 900 0
Bit 4
DDR_CSkw0 RW 1100 = 450 N/A 0
Bit 3
Reserved Reserved RW Reserved Reserved 0
Bit 2
Reserved Reserved RW Reserved Reserved 0
Bit 1
FBOUTSkw1 RW 00 = 0 10 = 500 0
Bit 0
FBOUTSkw0 RW 01 = 250 11 = 750 0
Pin # Name Control Function Type 0 1 Default
Bit 7
DDR_TSkw3 RW 0000 = 0 1101 = 600 0
Bit 6
DDR_TSkw2 RW 0100 = 150 1110 = 750 0
Bit 5
DDR_TSkw1 RW 1000 = 300 1111 = 900 0
Bit 4
DDR_TSkw0 RW 1100 = 450 N/A 0
Bit 3
Reserved Reserved RW Reserved Reserved 0
Bit 2
Reserved Reserved RW Reserved Reserved 0
Bit 1
Reserved Reserved RW Reserved Reserved 0
Bit 0
Reserved Reserved RW Reserved Reserved 0
-
-
-
-
B
y
te 8
-
-
-
-
B
y
te 7
-
-
-
-
DDR_C Skew Control
(also see table1)
-
-
-
Byte Count
Programming b(7:0)
Writing to this register will
configure how many bytes
will be read back, default is
0h = 15 bytes
I
2
C Table: Grou
p
Skew Control Re
g
ister
B
y
te 19
-
-
-
-
-
-
-
-
-
FB_OUT Skew Control
(also see table 2)
I
2
C Table: Grou
p
Skew Control Re
g
ister
B
y
te 20
-
DDR_T Skew Control
(also see table1)
-
-
-
-
-
-
-
P1-P3P4-P6P7-P9P10-P12

9P936AGLF

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Description:
Clock Buffer PC BUFFER
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