Atmel AT88SA10HS [DATASHEET] 10
8595H−CRYPTO−9/2012
5.2 IO Blocks
Commands are sent to the chip, and responses received from the chip, within a block
Byte Number
that is constructed in the following way:
Name Meaning
0 Count
Number of bytes to be transferred to the chip in the block, including count, packet and
checksum, so this byte should always have a value of (N+1). The maximum size block is 39 and
the minimum size block is four. Values outside this range will cause unpredictable operation.
1 to (N-2) Packet Command, parameters and data, or response. See Section 6 for more details.
N-1, N Checksum
CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the initial
register value should be zero and after the last
bit of the count and packet have been transmitted
the internal CRC register should have a value that matches that in the block. The first byte
transmitted (N-1) is the least significant byte of the CRC value so the last byte of the block is the
most significant byte of the CRC.
5.3 IO Flow
The general IO flow for the commands is as follows:
1. System sends Wake token
2. System sends transmit flag
3. Receive 0x11 value from AT88SA10HS to verify proper wakeup synchronization.
4. System sends command flag
5. System sends complete command block
6. System waits t
PARSE
for the AT88SA10HS to check for command formation errors
7. System sends transmit flag. If command format is OK, the AT88SA10HS ignores this flag because the computation
engine is busy. If there was an error, the AT88SA10HS responds with an error code
8. System waits t
EXEC
, see Section 5.1.1
9. System sends transmit flag
10. Receive output block from the AT88SA10HS, system checks CRC
11. If CRC from AT88SA10HS is incorrect, indicating transmission error, system resends transmit flag
12. System sends sleep flag to the AT88SA10HS
Where the command in question has a short execution delay the system should omit steps six, seven and eight and replace
this with a wait of duration t
PARSE
+ t
EXEC
.
5.4 Synchronization
Because the communications protocol is half duplex, there is the possibility that the system and the AT88SA10HS will fall out
of synchronization with each other. In order to speed recovery, AT88SA10HS implements a timeout that forces the
AT88SA10HS to sleep.
5.4.1 IO Timeout
After a leading transition for any data token has been received, AT88SA10HS will expect the remaining bits of the token to be
properly received by the chip within the t
TIMEOUT
interval. Failure to send enough bits or the transmission of an illegal token (a
low pulse exceeding t
ZLO
) will cause the chip to enter the sleep state after the t
TIMEOUT
interval.
The same timeout applies during the transmission of the command block. After the transmission of a legal command flag, the
IO timeout circuitry is enabled until the last expected data bit is received. Note that the timeout counter is reset after every
legal token, so the total time to transmit the command may exceed the t
TIMEOUT
interval while the time between bits may not.
In order to limit the active current if the AT88SA10HS is inadvertently awakened, the IO timeout circuitry is also enabled when
the AT88SA10HS receives a wake-up. If the first token does not come within the t
TIMEOUT
interval, the AT88SA10HS will go
back to the sleep mode without performing any operations.
The IO Timeout circuitry is disabled when the chip is busy executing a command.
