AD9754AR Datasheet AD9754ARUZRL7, AD9754ARUZ, AD9754ARZ | P10-P12

AD9754

–9–

REV. A

FUNCTIONAL DESCRIPTION

Figure 16 shows a simplified block diagram of the AD9754. The

AD9754 consists of a large PMOS current source array that is

capable of providing up to 20 mA of total current. The array

is divided into 31 equal currents that make up the five most

significant bits (MSBs). The next four bits or middle bits consist

of 15 equal current sources whose value is 1/16th of an MSB

current source. The remaining LSBs are binary weighted frac-

tions of the middle bits current sources. Implementing the

middle and lower bits with current sources, instead of an R-2R

ladder, enhances its dynamic performance for multitone or low

amplitude signals and helps maintain the DAC’s high output

impedance (i.e., >100 kΩ).

All of these current sources are switched to one or the other of

the two output nodes (i.e., IOUTA or IOUTB) via PMOS

differential current switches. The switches are based on a new

architecture that drastically improves distortion performance.

This new switch architecture reduces various timing errors and

provides matching complementary drive signals to the inputs of

the differential current switches.

The analog and digital sections of the AD9754 have separate

power supply inputs (i.e., AVDD and DVDD). The digital sec-

tion, which is capable of operating up to a 125 MSPS clock rate

and over +2.7 V to +5.5 V operating range, consists of edge-

triggered latches and segment decoding logic circuitry. The

analog section, which can operate over a +4.5 V to +5.5 V range

includes the PMOS current sources, the associated differential

switches, a 1.20 V bandgap voltage reference and a reference

control amplifier.

The full-scale output current is regulated by the reference con-

trol amplifier and can be set from 2 mA to 20 mA via an exter-

nal resistor, R

SET

. The external resistor, in combination with

both the reference control amplifier and voltage reference V

REFIO

sets the reference current I

REF

, which is mirrored over to the

segmented current sources with the proper scaling factor. The

full-scale current, I

OUTFS

, is 32 times the value of I

REF

DAC TRANSFER FUNCTION

The AD9754 provides complementary current outputs, IOUTA

and IOUTB. IOUTA will provide a near full-scale current out-

put, I

OUTFS

, when all bits are high (i.e., DAC CODE = 16383)

while IOUTB, the complementary output, provides no current.

The current output appearing at IOUTA and IOUTB is a func-

tion of both the input code and I

OUTFS

and can be expressed as:

IOUTA = (DAC CODE/16384) × I

OUTFS

(1)

IOUTB = (16383 – DAC CODE)/16384 × I

OUTFS

(2)

where DAC CODE = 0 to 16383 (i.e., Decimal Representation).

As mentioned previously, I

OUTFS

is a function of the reference

current I

REF

, which is nominally set by a reference voltage V

REFIO

and external resistor R

SET

. It can be expressed as:

OUTFS

= 32 × I

REF

(3)

where I

REF

= V

REFIO

SET

(4)

The two current outputs will typically drive a resistive load

directly or via a transformer. If dc coupling is required, IOUTA

and IOUTB should be directly connected to matching resistive

loads, R

LOAD

, that are tied to analog common, ACOM. Note

that R

LOAD

may represent the equivalent load resistance seen by

IOUTA or IOUTB as would be the case in a doubly terminated

50 Ω or 75 Ω cable. The single-ended voltage output appearing

at the IOUTA and IOUTB nodes is simply:

OUTA

= IOUTA × R

LOAD

(5)

OUTB

= IOUTB × R

LOAD

(6)

Note that the full-scale value of V

OUTA

and V

OUTB

should not

exceed the specified output compliance range to maintain speci-

fied distortion and linearity performance.

The differential voltage, V

DIFF

, appearing across IOUTA and

IOUTB is:

DIFF

= (IOUTA – IOUTB) × R

LOAD

(7)

Substituting the values of IOUTA, IOUTB and I

REF

; V

DIFF

can

be expressed as:

DIFF

= {(2 DAC CODE – 16383)/16384} ×

DIFF

= {(32 R

LOAD

SET

) × V

REFIO

(8)

DIGITAL DATA INPUTS

(

DB13–DB0

)

150pF

+1.20V REF

AVDD ACOM

REFLO

ICOMP

PMOS

CURRENT SOURCE

ARRAY

+5V

SEGMENTED SWITCHES

FOR DB13–DB5

LSB

SWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

SET

2kV

0.1mF

IOUTA

IOUTB

0.1mF

AD9754

SLEEP

LATCHES

REF

REFIO

CLOCK

OUTB

OUTA

LOAD

50V

OUTB

OUTA

LOAD

50V

DIFF

= V

OUTA

– V

OUTB

Figure 16. Functional Block Diagram

AD9754

–10–

REV. A

These last two equations highlight some of the advantages of

operating the AD9754 differentially. First, the differential op-

eration will help cancel common-mode error sources associated

with IOUTA and IOUTB such as noise, distortion and dc off-

sets. Second, the differential code-dependent current and

subsequent voltage, V

DIFF

, is twice the value of the single-

ended voltage output (i.e., V

OUTA

or V

OUTB

), thus providing

twice the signal power to the load.

Note that the gain drift temperature performance for a single-

ended (VOUTA and VOUTB) or differential output (V

DIFF

) of

the AD9754 can be enhanced by selecting temperature tracking

resistors for R

LOAD

and R

SET

due to their ratiometric relation-

ship as shown in Equation 8.

REFERENCE OPERATION

The AD9754 contains an internal 1.20 V bandgap reference

that can be easily disabled and overridden by an external

reference. REFIO serves as either an input or output, depending

on whether the internal or external reference is selected. If

REFLO is tied to ACOM, as shown in Figure 17, the internal

reference is activated, and REFIO provides a 1.20 V output. In

this case, the internal reference must be compensated externally

with a ceramic chip capacitor of 0.1 µF or greater from REFIO

to REFLO. Also, REFIO should be buffered with an external

amplifier having an input bias current less than 100 nA if any

additional loading is required.

150pF

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

+5V

REFIO

FS ADJ

2kV

0.1mF

AD9754

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

Figure 17. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to

AVDD. In this case, an external reference may then be applied

to REFIO as shown in Figure 18. The external reference may

provide either a fixed reference voltage to enhance accuracy and

drift performance or a varying reference voltage for gain control.

Note that the 0.1 µF compensation capacitor is not required

since the internal reference is disabled, and the high input im-

pedance (i.e., 1 MΩ) of REFIO minimizes any loading of the

external reference.

REFERENCE CONTROL AMPLIFIER

The AD9754 also contains an internal control amplifier that is

used to regulate the DAC’s full-scale output current, I

OUTFS

The control amplifier is configured as a V-I converter, as shown

in Figure 18, such that its current output, I

REF

, is determined by

150pF

+1.2V REF

AVDDREFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9754

EXTERNAL

REF

REFIO

SET

AVDD

REFERENCE

CONTROL

AMPLIFIER

REFIO

Figure 18. External Reference Configuration

the ratio of the V

REFIO

and an external resistor, R

SET

, as stated

in Equation 4. I

REF

is copied over to the segmented current

sources with the proper scaling factor to set I

OUTFS

as stated in

Equation 3.

The control amplifier allows a wide (10:1) adjustment span of

OUTFS

over a 2 mA to 20 mA range by setting IREF between

62.5 µA and 625 µA. The wide adjustment span of I

OUTFS

provides several application benefits. The first benefit relates

directly to the power dissipation of the AD9754, which is pro-

portional to I

OUTFS

(refer to the Power Dissipation section). The

second benefit relates to the 20 dB adjustment, which is useful

for system gain control purposes.

The small signal bandwidth of the reference control amplifier

is approximately 0.5 MHz. The output of the control amplifier

is internally compensated via a 150 pF capacitor that limits the

control amplifier small-signal bandwidth and reduces its output

impedance. Since the –3 dB bandwidth corresponds to the

dominant pole, and hence the time constant, the settling time of

the control amplifier to a stepped reference input response can

be approximated In this case, the time constant can be approxi-

mated to be 320 ns.

There are two methods in which I

REF

can be varied for a fixed

SET

. The first method is suitable for a single-supply system in

which the internal reference is disabled, and the common-mode

voltage of REFIO is varied over its compliance range of 1.25 V

to 0.10 V. REFIO can be driven by a single-supply amplifier or

DAC, thus allowing I

REF

to be varied for a fixed R

SET

. Since the

1.2V

150pF

+1.2V REF

AVDDREFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9754

REF

SET

AVDD

REF

OUT1

OUT2

AGND

DB7–DB0

AD7524

AD1580

0.1V TO 1.2V

Figure 19. Single-Supply Gain Control Circuit

AD9754

–11–

REV. A

input impedance of REFIO is approximately 1 MΩ, a simple,

low cost R-2R ladder DAC configured in the voltage mode

topology may be used to control the gain. This circuit is shown

in Figure 19 using the AD7524 and an external 1.2 V reference,

the AD1580.

The second method may be used in a dual-supply system in

which the common-mode voltage of REFIO is fixed, and I

REF

varied by an external voltage, V

, applied to R

SET

via an ampli-

fier. An example of this method is shown in Figure 25 in which

the internal reference is used to set the common-mode voltage

of the control amplifier to 1.20 V. The external voltage, V

, is

referenced to ACOM and should not exceed 1.2 V. The value of

SET

is such that I

REFMAX

and I

REFMIN

do not exceed 62.5 µA

and 625 µA, respectively. The associated equations in Figure 20

can be used to determine the value of R

SET

150pF

+1.2V REF

AVDDREFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9754

REF

1mF

REF

= (1.2 – V

)/R

SET

WITH V

REFIO

AND 62.5mA I

REF

625A

Figure 20. Dual-Supply Gain Control Circuit

ANALOG OUTPUTS

The AD9754 produces two complementary current outputs,

IOUTA and IOUTB, which may be configured for single-end

or differential operation. IOUTA and IOUTB can be converted

into complementary single-ended voltage outputs, V

OUTA

and

OUTB

, via a load resistor, R

LOAD

, as described in the DAC

Transfer Function section by Equations 5 through 8. The

differential voltage, V

DIFF

, existing between V

OUTA

and V

OUTB

can also be converted to a single-ended voltage via a transformer

or differential amplifier configuration.

Figure 21 shows the equivalent analog output circuit of the

AD9754 consisting of a parallel combination of PMOS differen-

tial current switches associated with each segmented current

source. The output impedance of IOUTA and IOUTB is deter-

mined by the equivalent parallel combination of the PMOS

switches and is typically 100 kΩ in parallel with 5 pF. Due to

the nature of a PMOS device, the output impedance is also

slightly dependent on the output voltage (i.e., V

OUTA

and V

OUTB

)

and, to a lesser extent, the analog supply voltage, AVDD, and

full-scale current, I

OUTFS

. Although the output impedance’s signal

dependency can be a source of dc nonlinearity and ac linearity

(i.e., distortion), its effects can be limited if certain precautions

are noted.

AD9754

AVDD

IOUTA IOUTB

LOAD

Figure 21. Equivalent Analog Output Circuit

IOUTA and IOUTB also have a negative and positive voltage

compliance range. The negative output compliance range of

–1.0 V is set by the breakdown limits of the CMOS process.

Operation beyond this maximum limit may result in a break-

down of the output stage and affect the reliability of the AD9754.

The positive output compliance range is slightly dependent on

the full-scale output current, I

OUTFS

. It degrades slightly from its

nominal 1.25 V for an I

OUTFS

= 20 mA to 1.00 V for an I

OUTFS

2 mA. Operation beyond the positive compliance range will

induce clipping of the output signal which severely degrades

the AD9754’s linearity and distortion performance.

For applications requiring the optimum dc linearity, IOUTA

and/or IOUTB should be maintained at a virtual ground via an

I-V op amp configuration. Maintaining IOUTA and/or IOUTB

at a virtual ground keeps the output impedance of the AD9754

fixed, significantly reducing its effect on linearity. However,

it does not necessarily lead to the optimum distortion perfor-

mance due to limitations of the I-V op amp. Note that the

INL/DNL specifications for the AD9754 are measured in

this manner using IOUTA. In addition, these dc linearity

specifications remain virtually unaffected over the specified

power supply range of +4.5 V to +5.5 V.

Operating the AD9754 with reduced voltage output swings at

IOUTA and IOUTB in a differential or single-ended output

configuration reduces the signal dependency of its output

impedance thus enhancing distortion performance. Although

the voltage compliance range of IOUTA and IOUTB extends

from –1.0 V to +1.25 V, optimum distortion performance is

achieved when the maximum full-scale signal at IOUTA and

IOUTB does not exceed approximately 0.5 V. A properly se-

lected transformer with a grounded center-tap will allow the

AD9754 to provide the required power and voltage levels to

different loads while maintaining reduced voltage swings at

IOUTA and IOUTB. DC-coupled applications requiring a

differential or single-ended output configuration should size

LOAD

accordingly. Refer to Applying the AD9754 section for

examples of various output configurations.

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AD9754AR

Mfr. #:

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Digital to Analog Converters - DAC 14-Bit 100 MSPS

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AD9754AR

AD9754AR

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