DYNAMIC SPECIFICATIONS
Parameter Min Typ Max Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
) 125 MSPS
Output Settling Time (t
ST
) (to 0.1%)
1
35 ns
Output Propagation Delay (t
PD
)1ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
1
2.5 ns
Output Fall Time (10% to 90%)
1
2.5 ns
Output Noise (I
OUTFS
= 20 mA) 50 pA/Hz
Output Noise (I
OUTFS
= 2 mA) 30 pA/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
0 dBFS Output
T
A
= +25°C 75 86 dBc
–6 dBFS Output 86 dBc
–12 dBFS Output 78 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz 82 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 2.51 MHz 81 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz 77 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 20.2 MHz 63 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 10 MHz 68 73 dBc
Spurious-Free Dynamic Range within a Window
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz; 2 MHz Span 84 93 dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span 86 dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span 86 dBc
Total Harmonic Distortion
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
T
A
= +25°C –83 –75 dBc
f
CLOCK
= 50 MHz; f
OUT
= 2.00 MHz –78 dBc
f
CLOCK
= 100 MHz; f
OUT
= 2.00 MHz –78 dBc
Multitone Power Ratio (8 Tones at 110 kHz Spacing)
f
CLOCK
= 20 MSPS; f
OUT
= 2.00 MHz to 2.99 MHz
0 dBFS Output 85 dBc
–6 dBFS Output 84 dBc
–12 dBFS Output 87 dBc
–18 dBFS Output 88 dBc
NOTES
1
Measured single-ended into 50 load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Differential Transformer Coupled Output,
50 Doubly Terminated, unless otherwise noted)
AD9754
–3–
REV. A
AD9754
–4–
REV. A
ABSOLUTE MAXIMUM RATINGS*
With
Parameter Respect to Min Max Units
AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
ICOMP ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 AVDD +0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Descriptions Options*
AD9754AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9754ARU –40°C to +85°C 28-Lead TSSOP RU-28
AD9754-EB Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOIC
θ
JA
= 71.4°C/W
θ
JC
= 23°C/W
28-Lead TSSOP
θ
JA
= 97.9°C/W
θ
JC
= 14.0°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9754 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise noted)
DIGITAL SPECIFICATIONS
Parameter Min Typ Max Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
1
3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V
1
0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
S
) 2.0 ns
Input Hold Time (t
H
) 1.5 ns
Latch Pulsewidth (t
LPW
) 3.5 ns
NOTES
1
When DVDD = +5 V and Logic 1 voltage 3.5 V and Logic 0 voltage ≈1.3 V, IVDD can increase by up to 10 mA depending on f
CLOCK
.
Specifications subject to change without notice.
0.1%
0.1%
t
S
t
H
t
PD
t
ST
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
t
LPW
Figure 1. Timing Diagram
WARNING!
ESD SENSITIVE DEVICE
AD9754
–5–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin No. Name Description
1 DB13 Most Significant Data Bit (MSB).
2–13 DB12–DB1 Data Bits 1–12.
14 DB0 Least Significant Data Bit (LSB).
15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if
not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19, 25 NC No Connect.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
24 AVDD Analog Supply Voltage (+4.5 V to +5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on positive edge of clock.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9754
NC = NO CONNECT
(MSB) DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
(LSB) DB0
CLOCK
DVDD
DCOM
NC
AVDD
ICOMP
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP

AD9754AR

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 14-Bit 100 MSPS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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