DS2141A
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DS2141A FEATURES
Parallel control port
Large error counters
Onboard dual 2-frame elastic store
FDL support circuitry
Robbed-bit signaling extraction and insertion
Programmable output clocks
Fully independent transmit and receive sections
Frame sync generation
Error-tolerant yellow and blue alarm detection
Output pin test mode
Payload loopback capability
SLC-96 support
Remote loop up/down code detection
Loss of transmit clock detection
Loss of receive clock detection
1's density violation detection
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE DESCRIPTION
1TCLK ITransmit Clock. 1.544 MHz primary clock.
2TSER ITransmit Serial Data. Transmit NRZ serial data, sampled on the
falling edge of TCLK.
3TCHCLKOTransmit Channel Clock. 192 kHz clock which pulses high during
the LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking
clocks in DDS applications. See Section 13 for timing details.
4
5
TPOS
TNEG
O Transmit Bipolar Data. Updated on rising edge of TCLK.
6-13 AD0-AD7 I/O Address/Data Bus. An 8-bit multiplexed address/data bus.
14 BTS I Bus Type Select. Strap high to select Motorola bus timing; strap
low to select Intel bus timing. This pin controls the function of
RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins
assume the function listed in parentheses ().
15
RD (DS)
I
Read Input (Data Strobe).
16 CS I Chip Select. Must be low to read or write the port.
17 ALE(AS) I Address Latch Enable (Address Strobe). A positive-going edge
serves to demultiplex the bus.
18
WR (R/ W )
I
Write Input (Read/Write).
19 RLINK O Receive Link Data. Updated with either FDL data (ESF) or Fs-bits
(D4) or Z-bits (ZBTSI) one RCLK before the start of a frame. See
Section 13 for timing details.
20 VSS - Signal Ground. 0.0 volts.
21 RLCLK O Receive Link Clock. 192 kHz clock which pulses high during the
LSB of each channel. Useful for parallel-to-serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking
clocks in DDS applications. See Section 13 for timing details.
22 RCLK I Receive Clock. 1.544 MHz primary clock.
