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DS2141AQ+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
DS2141A
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TCR2: TRANSMIT CONTROL REGISTER 2 (36h)
(MSB) (LSB)
TESTM TESTIO TZBTSI TSDW TSM TSIO TD4YM B7ZS
SYMBOL POSITION NAME AND DESCRIPTION
TESTM TCR2.7 Test Mode Select. Set this bit to a 1 to force all outputs
(including I/O pins) either high (TCR2.6 = 1) or low (TCR2.6 =
0).
TESTIO TCR2.6
Test I/O Pins.
0=force all output (and I/O) pins to a logic 0.
1=force all output (and I/O) pins to a logic 1.
TZBTSI TCR2.5
Transmit Side ZBTSI Enable.
0=ZBTSI disabled.
1=ZBTSI enabled.
TSDW TCR2.4
TSYNC Double-Wide.
0=do not pulse double-wide in signaling frames.
1=do pulse double-wide in signaling frames.
(note: this bit must be set to 0 when TCR 2.3 = 1 or when
TCR2.2 = 0).
TSM TCR2.3
TSYNC Mode Select.
0=frame mode (see the timing in Section 13).
1=multiframe mode (see the timing in Section 13).
TSIO TCR2.2
TSYNC I/O Select.
0=TSYNC is an input.
1=TSYNC is an output.
TD4YM TCR2.1
Transmit Side D4 Yellow Alarm Select.
0=0s in bit 2 of all channels.
1=a 1 in the S-bit position of frame 12.
B7ZS TCR2.0
Bit 7 Zero Suppression Enable.
0=no stuffing occurs.
1=Bit 7 forced to a 1 in channels with all 0s.
DS2141A
11 of 39
CCR1: COMMON CONTROL REGISTER 1 (37h)
(MSB) (LSB)
TESE P34F RSAO - SCLKM RESE PLB LLB
SYMBOL POSITION NAME AND DESCRIPTION
TESE CCR1.7
Transmit Elastic Store Enable.
0=elastic store is bypassed.
1=elastic store is enabled.
P34F CCR1.6
Function of Pin 34.
0=Receive Loss of Sync (RLOS).
1=Loss of Transmit Clock (LOTC).
RSAO CCR1.5
Receive Signaling All 1's.
0=allow robbed signaling bits to appear at RSER.
1=force all robbed signaling bits at RSER to 1.
- CCR1.4 Not Assigned. Should be set to 0 when written to.
SCLKM CCR1.3
SYSCLK Mode Select.
0=if SYSCLK is 1.544 MHz.
1=if SYSCLK is 2.048 MHz.
RESE CCR1.2
Receive Elastic Store Enable.
0=elastic store is bypassed.
1=elastic store is enabled.
PLB CCR1.1
Payload Loopback.
0=loopback disabled.
1=loopback enabled.
LLB CCR1.0
Local Loopback.
0=loopback disabled.
1=loopback enabled.
PAYLOAD LOOPBACK
When CCR1.1 is set to a 1, the DS2141A will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2141A will
loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit
section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are
reinserted by the DS2141A. When PLB is enabled, the following will occur:
1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK.
2. All of the receive side signals will continue to operate normally.
3. The TCHCLK and TCHBLK signals are forced low.
4. Data at the TSER pin is ignored.
5. The TLCLK signal will become synchronous with RCLK instead of TCLK.
DS2141A
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LOCAL LOOPBACK
When CCR1.0 is set to a 1, the DS2141A will enter a Local LoopBack (LLB) mode. This loopback is
useful in testing and debugging applications. In LLB, the DS2141A will loop data from the transmit side
back to the receive side. This loopback is synonymous with replacing the RCLK input with the TCLK
signal, and the RPOS/RNEG inputs with the TPOS/TNEG outputs. When LLB is enabled, the following
will occur:
1. The TPOS and TNEG pins will transmit an unframed all 1's.
2. Data at RPOS and RNEG will be ignored.
3. All receive side signals will take on timing synchronous with TCLK instead of RCLK.
CCR1: COMMON CONTROL REGISTER 2 (38h)
(MSB) (LSB)
TFM TB8ZS TSLC96 TFDL RFM RB8ZS RSLC96 RFDL
SYMBOL POSITION NAME AND DESCRIPTION
TFM CCR2.7
Transmit Frame Mode Select.
0=D4 framing mode.
1=ESF framing mode.
TB8ZS CCR2.6
Transmit B8ZS Enable.
0=B8ZS disabled.
1=B8ZS enabled.
TSLC96 CCR2.5
Transmit SLC-96/Fs Bit Insertion Enable.
0=SLC-96 disabled.
1=SLC-96 enabled.
TFDL CCR2.4
Transmit Zero Stuffer Enable.
0=zero stuffer disabled.
1=zero stuffer enabled.
RFM CCR2.3
Receive Frame Mode Select.
0=D4 framing mode.
1=ESF framing mode.
RB8ZS CCR2.2
Receive B8ZS Enable.
0=B8ZS disabled.
1=B8ZS enabled.
RSLC96 CCR2.1
Receive SLC-96 Enable.
0=SLC-96 disabled.
1=SLC-96 enabled.
RFDL CCR2.0
Receive Zero Destuffer Enable.
0=zero destuffer disabled.
1=zero destuffer enabled.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

DS2141AQ+

Mfr. #:
Buy DS2141AQ+
Manufacturer:
Maxim Integrated
Description:
Telecom Interface ICs T1 Controller w/Elastic Store
Lifecycle:
New from this manufacturer.
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