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DS2141AQ+

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DS2141A
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5.0 ERROR COUNT REGISTERS
There is a set of three counters in the DS2141A that record bipolar violations, errors in the CRC6 code
words, and frame bit errors. Each of these three counters is automatically updated on 1-second boundaries
as determined by the 1-second timer in Status Register 2 (SR2.5). Hence, these registers contain
performance data from the previous second. The user can use the interrupt from the 1-second timer to
determine when to read these registers. The user has a full second to read the counters before the data is
lost.
BPVCR1: BIPOLAR VIOLATION COUNT REGISTER 1 (23h)
BPVCR2: BIPOLAR VIOLATION COUNT REGISTER 2 (24h)
(MSB) (LSB)
BV15 BV14 BV13 BV12 BV11 BV10 BV9 BV8 BPVCR1
BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0 BPVCR2
SYMBOL POSITION NAME AND DESCRIPTION
BV15 BPVCR1.7 MSB of the bipolar violation count.
BV0 BPVCR2.0 LSB of the bipolar violation count.
Bipolar Violation Count Register 1 (BPVCR1) is the most significant word and BPVCR2 is the least
significant word of a 16-bit counter that records bipolar violations (BPVs). If the B8ZS mode is set for
the receive side via CCR2.2, then B8ZS code words are not counted. This counter increments at all times
and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not roll over. If the
DS2141A is programmed to record ESF error events (RCR2.0=1), then the BPVCR will increment for
each ESF multiframe that contains either an error in the CRC6 word or an out-of-frame occurrence (loss
of sync).
CRCCR1: CRC6 COUNT REGISTER 1 (25h)
CRCCR2: CRC6 COUNT REGISTER 2 (26h)
(MSB) (LSB)
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 CRCCR1
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 CRCCR2
SYMBOL POSITION NAME AND DESCRIPTION
CRC7 CRCCR1.7 MSB of the CRC6 count.
CRC0 CRCCR2.0 LSB of the CRC6 count.
CRC6 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 16-bit counter that records word errors in the Cyclic Redundancy Check 6 (CRC6) when the
DS2141A is operated in the ESF framing mode (CCR2.3 = 1). This counter saturates at 65,535 and will
not roll over. The counter is disabled during loss of sync conditions.
DS2141A
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FECR: FRAME ERROR COUNT REGISTER (27h)
(MSB) (LSB)
FE7 FE6 FE5 FE4 FE3 FE2 FE1 FE0
SYMBOL POSITION NAME AND DESCRIPTION
FE7 FECR.7 MSB of the Frame Error count.
FE0 FECR.0 LSB of the Frame Error count.
The Frame Error Count Register (FECR) is a 8-bit counter that records either errors in the framing
pattern. The FECR will count individual bit errors in the ESF framing pattern (...001011...) if the device
is set into the ESF framing mode (CCR2.3 = 1) and it will count individual bit errors in the Ft framing
pattern (...101010...) in the D4 framing mode (CCR2.3 = 0). If RCR2.1=1, then the FECR will also record
individual bit errors in the Fs framing pattern (...001110...) when it is in the D4 framing mode. This
counter saturates at 255 and will not roll over. The counter is disabled during loss of sync conditions.
6.0 FDL/FS EXTRACTION AND INSERTION
The DS2141A has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF
framing mode and from/into Fs-bit position in the D4 framing mode. Since SLC-96 utilizes the Fs-bit
position, this capability can also be used in SLC-96 applications. The operation of the receive and
transmit sections will be discussed separately.
6.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 x 250 µs). The DS2141A
will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4,
the INT2 pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms
to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the
RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT2 pin will toggled low if
enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern until
an important event occurs.
The DS2141A also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follow a subset of a LAPD protocol. The LAPD protocol
states that no more than five 1's should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2141A
will automatically look for five 1's in a row, followed by a 0. If it finds such a pattern, it will
automatically remove the 0. If the 0 destuffer sees six or more 1's in a row followed by a 0, the 0 is not
removed. The CCR2.0 bit should always be set to a 1 when the DS2141A is extracting the FDL. More on
how to use the DS2141A in FDL applications is covered in a separate Application Note.
DS2141A
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RFDL: RECEIVE FDL REGISTER (28h)
(MSB) (LSB)
RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0
SYMBOL POSITION NAME AND DESCRIPTION
RFDL7 RFDL.7 MSB of the Received FDL Code.
RFDL0 RFDL.0 LSB of the Received FDL Code.
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs-
bits. The LSB is received first.
RFDLM1: RECEIVE FDL MATCH REGISTER 1 (29h)
RFDLM2: RECEIVE FDL MATCH REGISTER 2 (2Ah)
(MSB) (LSB)
RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0
SYMBOL POSITION NAME AND DESCRIPTION
RFDL7 RFDL.7 MSB of the FDL Match Code.
RFDL0 RFDL.0 LSB of the FDL Match Code.
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RFDLM1/RFDLM2), RSR2.2 will be set to a 1 and the INT2 will go active if enabled via IMR2.2.
6.2 Transmit Section
The transmit section will shift out either the FDL (in the ESF framing mode) or the Fs-bits (in the D4
framing mode) contained in the Transmit FDL register (TFDL) into the T1 data stream. When a new
value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the
outgoing T1 data stream. After the full 8 bits have been shifted out, the DS2141A will signal the host
microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The
INT2 will also toggle low if enabled via IMR2.3. The user has 2 ms (1.5 ms in SLC-96 applications) to
update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be
transmitted once again.
The DS2141A also contains a 0 stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states
that no more than five 1's should be transmitted in a row so that the data does not resemble an opening or
closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2141A will
automatically look for five 1's in a row. If it finds such a pattern, it will automatically insert a 0 after the
five 1's. The CCR2.0 bit should always be set to a 1 when the DS2141A is inserting the FDL. More on
how to use the DS2141A in FDL applications is covered in a separate Application Note.
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DS2141AQ+

Mfr. #:
Buy DS2141AQ+
Manufacturer:
Maxim Integrated
Description:
Telecom Interface ICs T1 Controller w/Elastic Store
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