P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet Rev. 01 — 5 September 2005 31 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.21 SPI
The P89LPC9401 provides another high-speed serial communication interface—the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in
Master mode or up to 3 Mbit/s in Slave mode. It has a transfer completion flag and write
collision flag protection.
The SPI interface has three pins: SPICLK, MOSI, MISO and SS:
• SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
Typical connections are shown in Figure 12 through Figure 14.
Fig 11. SPI block diagram
002aab466
CPU clock
DIVIDER
BY 4, 16, 64, 128
SELECT
CLOCK LOGIC
SPI CONTROL REGISTER
READ DATA BUFFER
8-BIT SHIFT REGISTER
SPI CONTROL
SPI STATUS REGISTER
SPR1
SPIF
WCOL
SPR0
SPI clock (master)
PIN
CONTROL
LOGIC
S
M
S
M
M
S
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SPI
interrupt
request
internal
data
bus
SSIG
SPEN
SPEN
MSTR
DORD
MSTR
CPHA
CPOL
SPR1
SPR0
MSTR
SPEN
clock
