P89LPC9401_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet Rev. 01 — 5 September 2005 46 of 59
Philips Semiconductors
P89LPC9401
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
10. Dynamic characteristics
Table 12: Dynamic characteristics (12 MHz)
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1] [2]
Symbol Parameter Conditions Variable clock f
osc
= 12 MHz Unit
Min Max Min Max
f
osc(RC)
internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz
f
osc(WD)
internal watchdog oscillator
frequency
320 520 320 520 kHz
f
osc
oscillator frequency 0 12 - - MHz
T
cy(CLK)
clock cycle time see Figure 18 83 - - - ns
f
CLKLP
active frequency on pin CLKLP 0 8 - - MHz
Glitch filter
t
gr
glitch rejection P1.5/RST pin - 50 - 50 ns
any pin except
P1.5/
RST
- 15 - 15 ns
t
sa
signal acceptance time P1.5/RST pin 125 - 125 - ns
any pin except
P1.5/
RST
50 - 50 - ns
External clock
t
CHCX
clock HIGH time see Figure 18 33 T
cy(CLK)
− t
CLCX
33 - ns
t
CLCX
clock LOW time see Figure 18 33 T
cy(CLK)
− t
CHCX
33 - ns
t
CLCH
clock rise time see Figure 18 -8-8ns
t
CHCL
clock fall time see Figure 18 -8-8ns
Shift register (UART mode 0)
T
XLXL
serial port clock cycle time see Figure 17 16T
cy(CLK)
- 1333 - ns
t
QVXH
output data set-up to clock rising
edge time
see Figure 17 13T
cy(CLK)
- 1083 - ns
t
XHQX
output data hold after clock rising
edge time
see Figure 17 -T
cy(CLK)
+ 20 - 103 ns
t
XHDX
input data hold after clock rising edge
time
see Figure 17 -0-0ns
t
XHDV
input data valid to clock rising edge
time
see Figure 17 150 - 150 - ns
SPI interface
f
SPI
SPI operating frequency
slave 0
CCLK
⁄
6
0 2.0 MHz
master -
CCLK
⁄
4
- 3.0 MHz
T
SPICYC
SPI cycle time see Figure 19,
20, 21, 22
slave
6
⁄
CCLK
- 500 - ns
master
4
⁄
CCLK
- 333 - ns
t
SPILEAD
SPI enable lead time (slave) see Figure 21,
22
250 - 250 - ns
t
SPILAG
SPI enable lag time (slave) see Figure 21,
22
250 - 250 - ns
