AD7811/AD7812
–16–
REV. B
RFS. The first rising SCLK edge after the rising edge of the
RFS signal causes DOUT to leave its high impedance state and
data is clocked out onto the DOUT line and also on subsequent
SCLK rising edges. The DOUT pin goes back into a high
impedance state on the 11th SCLK rising edge—Point “A” on
Figure 18. A minimum of 11 SCLKs are therefore needed to
carry out a serial read. Data on the DIN line is latched in on
the first SCLK falling edge after the falling edge of the TFS
signal and on subsequent SCLK falling edges. The control
register is updated on the 13th SCLK rising edge—point “B” on
Figure 18. A minimum of 13 SCLK pulses are therefore needed
to complete a serial write operation. In multipackage applications
the RFS and TFS signals can be used as chip select signals. The
serial interface will not shift data in or out until it receives the
active edge of the RFS or TFS signal.
Simplifying the Serial Interface
The five-wire interface is designed to support many different
serial interface standards. However, it is possible to reduce the
number of lines required to just three. By simply connecting the
TFS and RFS pins to the CONVST signal (see Figure 4), the
CONVST signal can be used to enable the serial port for read-
ing and writing. This is only possible where a noncontinuous
serial clock is being used.
MICROPROCESSOR INTERFACING
The serial interface on the AD7811 and AD7812 allows the
parts to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7811 and AD7812 with some of the more common micro-
controller and DSP serial interface protocols.
AD7811/AD7812 to PIC16C6x/7x
The PIC16C6x Synchronous Serial Port (SSP) is configured as
an SPI Master with the Clock Polarity bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
Figure 19 shows the hardware connections needed to interface
to the PIC16/17. In this example I/O port RA1 is being used to
pulse CONVST and enable the serial port of the AD7811/
AD7812. This microcontroller transfers only eight bits of data
during each serial transfer operation; therefore, two consecutive
read/write operations are needed.
CONVST
AD7811/AD7812*
DOUT
DIN
SCLK
RFS
TFS
PIC16C6x/7x*
SCK/RC3
SDO/RC5
SDI/ RC4
RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Interfacing to the PIC16/17
AD7811/AD7812 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 0), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 user manual. A connection diagram is shown in
Figure 20.
CONVST
AD7811/AD7812*
DOUT
DIN
SCLK
RFS
TFS
MC68HC11*
SCLK/PD4
MISO/PD2
MOSI/PD3
PA0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to the MC68HC11
AD7811/AD7812 to 8051
The AD7811/AD7812 requires a clock synchronized to the
serial data. The 8051 serial interface must therefore be operated
in Mode 0. In this mode serial data enters and exits through
RxD and a shift clock is output on TxD (half duplex). Figure 21
shows how the 8051 is connected to the AD7811/AD7812.
However, because the AD7811/AD7812 shifts data out on the
rising edge of the shift clock and latches data in on the falling
edge, the shift clock must be inverted.
AD7811/AD7812*
DOUT
DIN
SCLK
TFS
8051*
TxD
RxD
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
RFS
Figure 21. Interfacing to the 8051 Serial Port
C
AD7811/AD7812
–17–REV. B
It is possible to implement a serial interface using the data ports
on the 8051. This would also allow a full duplex serial transfer
to be implemented. The technique involves “bit banging” an
I/O port (e.g., P1.0) to generate a serial clock and using two
other I/O ports (e.g., P1.1 and P1.2) to shift data in and out—
see Figure 22.
AD7811/AD7812*
DOUT
DIN
SCLK
RFS
TFS
8051*
P1.0
P1.1
P1.2
P1.3
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Interfacing to the 8051 Using I/O Ports
AD7811/AD7812 to TMS320C5x
The serial interface on the TMS320C5x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7811. Frame synchronization inputs have been supplied on
the AD7811/AD7812 to allow easy interfacing with no extra
gluing logic. The serial port of the TMS320C5x is set up to
operate in Burst Mode with internal CLKX (Tx serial clock)
and FSX (Tx frame sync). The Serial Port Control register
(SPC) must have the following setup: F0 = 0, FSM = 1,
MCM = 1 and TXM = 1. The connection diagram is shown
in Figure 23.
AD7811/AD7812*
DOUT
SCLK
RFS
TFS
TMS320C5x*
CLKX
CLKR
FSX
*ADDITIONAL PINS OMITTED FOR CLARITY
FSR
DR
DIN DT
Figure 23. Interfacing to the TMS320C5x
AD7811/AD7812 to ADSP-21xx
The ADSP-21xx family of DSPs are easily interfaced to the
AD7811/AD7812 without the need for extra gluing logic. The
SPORT is operated in normal framing mode. The SPORT
control register should be set up as follows:
TFSW = RFSW = 0, Normal Framing
INVRFS = INVTFS = 0, Active High Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1001, 10-Bit Data Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, External Framing Signal
ITFS = 1, Internal Framing Signal
The 10-bit data words will be right justified in the 16-bit serial
data registers when using this configuration. Figure 24 shows
the connection diagram.
AD7811/AD7812*
DOUT
DIN
SCLK
RFS
TFS
ADSP-21xx*
SCLK
DR
DT
RFS
*ADDITIONAL PINS OMITTED FOR CLARITY
TFS
Figure 24. Interfacing to the ADSP-21xx
AD7811/AD7812 to DSP56xxx
The connection diagram in Figure 25 shows how the AD7811
and AD7812 can be connected to the SSI (Synchronous Serial
Interface) of the DSP56xxx family of DSPs from Motorola. The
SSI is operated in Synchronous Mode (SYN bit in CRB =1)
with internally generated 1-bit clock period frame sync for both
Tx and Rx (FSL1 and FSL0 bits in CRB = 1 and 0 respectively).
AD7811/AD7812*
DOUT
SCLK
DSP56xxx*
SCK
SRD
*ADDITIONAL PINS OMITTED FOR CLARITY
DIN
STD
SC2RFS
TFS
Figure 25. Interfacing to the DSP56xxx
C
AD7811/AD7812
OUTLINE DIMENSIONS
Fig
ure 1. 16-Lead Plastic Dual Inline Package [PDIP]
Narrow Body
N-16
Dimensions measured in inches
Figure 2.
16-Lead Standard Small Outline Package [SOIC-N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MS-001-BB
0.022
0.018
0.014
0.150
0.130
0.115
0.070
0.060
0.045
16
1
8
9
0.100
BSC
0.775
0.755
0.735
0.210
MAX
0.015
MIN
0.005
MIN
0.280
0.250
0.240
0.060
MAX
0.430
MAX
0.014
0.010
0.008
0.325
0.310
0.300
0.015
GAUGE
PLANE
0.195
0.130
0.115
02-13-2014-C
SEATING
PLANE
TOP VIEW
SIDE VIEW
END VIEW
PIN 1
INDICATOR
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16
9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
060606-A
45°
--18--
REV. C

AD7811YRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10-Bit 4-Ch 350kSPS Serial
Lifecycle:
New from this manufacturer.
Delivery:
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