AD7811/AD7812
–4–
REV. B
ABSOLUTE MAXIMUM RATINGS*
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND (CONVST, SCLK, RFS, TFS,
DIN, A0) . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to DGND (DOUT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
REF
IN
to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Analog Inputs
V
IN1
–V
IN4
(AD7811) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
IN1
–V
IN8
(AD7812) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C
ORDERING GUIDE
Linearity Package Package
Model Error Descriptions Options
AD7811YN ± 1 LSB 16-Lead Plastic DIP N-16
AD7811YR ± 1 LSB 16-Lead Small Outline IC (SOIC) R-16A
AD7811YRU ± 1 LSB 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD7812YN ± 1 LSB 20-Lead Plastic DIP N-20
AD7812YR ± 1 LSB 20-Lead Small Outline IC (SOIC) R-20A
AD7812YRU ± 1 LSB 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7811/AD7812 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Z
1
Z
C
AD7811/AD7812
–5–REV. B
PIN FUNCTION DESCRIPTIONS
Pin(s) Pin(s)
AD7811 AD7812 Mnemonic Description
11 V
REF
An external reference input can be applied here. When using an external precision
reference or V
DD
the EXTREF bit in the control register must be set to logic one. The
external reference input range is 1.2 V to V
DD
.
22 C
REF
Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise
performance of the on-chip reference.
3, 5–7 3, 5–11 V
IN1
–V
IN4(8)
Analog Inputs. The analog input range is 0 V to V
REF
.
4 4 AGND Analog Ground. Ground reference for track/hold, comparator, on-chip reference and
DAC.
8 12 A0 Package Address Pin. This Logic Input can be hardwired high or low. When used in
conjunction with the package address bit in the control register this input allows two
devices to share the same serial bus. For example a twelve channel solution can be
achieved by using the AD7811 and the AD7812 on the same serial bus.
9 13 DGND Digital Ground. Ground reference for digital circuitry.
10 14 TFS Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new
control byte should be shifted in on the next 10 falling edges of SCLK.
11 15 RFS Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in
the serial interface. It is used to provide compatibility with DSPs which use a continuous
serial clock and framing signal. In multipackage applications the RFS Pin can also be
used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a
rising edge on this input. The counter is reset at the end of a serial read operation.
12 16 DOUT Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial
clock. The output enters a High impedance condition on the rising edge of the 11th
SCLK pulse.
13 17 DIN Serial Data Input. The control byte is read in at this input. In order to complete a
serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are
shifted in—see Serial Interface section.
14 18 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data
from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is
clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK.
15 19 CONVST Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold
Mode on the falling edge of this signal and a conversion is initiated. The state of this
pin at the end of conversion also determines whether the part is powered down or not.
See operating modes section of this data sheet.
16 20 V
DD
Positive Supply Voltage 2.7 V to 5.5 V.
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7811
V
REF
DIN
SCLK
CONVST
V
DD
C
REF
V
IN1
AGND
TFS
RFS
DOUT
V
IN2
V
IN3
V
IN4
A0
DGND
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7812
V
REF
DIN
SCLK
V
DD
C
REF
V
IN1
AGND
TFS
RFS
DOUT
V
IN2
V
IN3
V
IN4
V
IN5
V
IN6
V
IN7
V
IN8
A0
DGND
CONVST
C
AD7811/AD7812
–6–
REV. B
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distor-
tion) ratio for an ideal N-bit converter with a sine wave input
is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 10-bit converter, this is 62 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7811 and AD7812
it is defined as:
THD (dB) = 20 log
V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it will
be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7811 and AD7812 are tested using the CCIF standard
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the inter-
modulation distortion is as per the THD specification where it is
the ratio of the rms sum of the individual distortion products to
the rms amplitude of the fundamental expressed in dBs.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale 20 kHz sine wave signal to all nonselected input channels
and determining how much that signal is attenuated in the selected
channel. The figure given is the worst case across all four or
eight channels for the AD7811 and AD7812 respectively.
Relative Accuracy
Relative accuracy, or endpoint nonlinearity, is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (0000 . . . 000)
to (0000 ...001) from the ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the difference in Offset Error between any two channels.
Gain Error
This is the deviation of the last code transition (1111 . . . 110)
to (1111 ...111) from the ideal, i.e., V
REF
– 1 LSB, after the
offset error has been adjusted out.
Gain Error Match
This is the difference in Gain Error between any two channels.
Track/Hold Acquisition Time
Track/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
± 1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where a change in the selected input channel takes place or
where there is a step input change on the input voltage applied
to the selected V
IN
input of the AD7811 or AD7812. It means
that the user must wait for the duration of the track/hold acquisi-
tion time after the end of conversion or after a channel change/
step input change to V
IN
before starting another conversion, to
ensure that the part operates to specification.
C

AD7811YRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 10-Bit 4-Ch 350kSPS Serial
Lifecycle:
New from this manufacturer.
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