AD7811/AD7812
–8–
REV. B
Control Register (AD7812)
The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7812 receives a falling
edge on its TFS pin. The AD7812 will maintain the same configuration until a new control byte is written to the part. The control
register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is
being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros;
therefore, when the supplies are connected, the AD7812 is powered down by default.
Control Register AD7812
9 0
0A1DP0DPV
8NI
/ DNGA /FFID LGS 2HC1HC0HC
TSVNOC
FERTXE
A0 This is the package address bit. It is used in conjunction with the package address pin to allow two AD7812s to
share the same serial bus. The AD7812 can also share the same serial bus with the AD7811. When a control word
is written to the control register of the AD7812 the control word is ignored if the package address bit in the con-
trol byte does not match how the package address pin is hardwired. Only the serial port of the device which
received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus
on the next serial read. When the part powers up this bit is set to 0.
PD1, PD0 These bits allow the AD7812 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and
PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the
power-down mode when the AD7812 enters a power-down at the end of a conversion. There are two power-down
modes—Full Power-Down and Partial Power-Down. See Power-Down section of this data sheet.
PD1 PD0 Description
0 0 Full Power-Down of the AD7812
0 1 Partial Power-Down at the End of Conversion
1 0 Full Power-Down at the End of Conversion
1 1 Power-Up the AD7812
V
IN8
/AGND The DIF/SGL bit in the control register must be set to 0 in order to use this option otherwise this bit is ignored.
Setting V
IN8
/AGND to 0 configures the analog inputs of the AD7812 as eight single-ended analog inputs
referenced to analog ground (AGND). By setting this bit to 1 the input channels V
IN1
to V
IN7
are configured
as seven pseudo differential channels with respect to V
IN8
—see Table II.
DIF/SGL This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0
the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to
V
IN8
as explained above. Setting this bit to 1 configures the analog input channels as four pseudo differential pairs
V
IN1
/V
IN2
, V
IN3
/V
IN4
, V
IN5
/V
IN6
and V
IN7
/V
IN8
—see Table II.
CH2, CH1, CH0 These bits are used in conjunction with V
IN8
/AGND and DIF/SGL to select an analog input channel. Table II
shows how the various channel selections are made.
CONVST Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control
register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initi-
ated in the same write operation. The bit is reset after the end of a conversion.
EXTREF This bit must be set to a logic one if the user wishes to use an external reference or use V
DD
as the reference.
When the external reference is selected the on-chip reference circuitry powers down and the current consumption
is reduced by about 1 mA.
