12-Bit CCD Signal Processor with
Precision Timing
Core
AD9949
Rev. B
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FEATURES
New AD9949A supports CCD line length > 4096 pixels
Correlated double sampler (CDS)
0 dB to 18 dB pixel gain amplifier (PxGA®)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit, 36 MSPS analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing driver
Precision Timing™ core with < 600 ps resolution
On-chip 3 V horizontal and RG drivers
40-lead LFCSP package
APPLICATIONS
Digital still cameras
High speed digital imaging applications
GENERAL DESCRIPTION
The AD9949 is a highly integrated CCD signal processor for
digital still camera applications. Specified at pixel rates of up to
36 MHz, the AD9949 consists of a complete analog front end
with A/D conversion, combined with a programmable timing
driver. The Precision Timing core allows adjustment of high
speed clocks with < 600 ps resolution.
The analog front end includes black level clamping, CDS,
PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver
provides the high speed CCD clock drivers for RG and H1 to
H4. Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving, 40-lead LFCSP package, the
AD9949 is specified over an operating temperature range of
−20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
CLAMP
DOUT
CCDIN
REFT REFB
INTERNAL
REGISTERS
6dB TO 42dB
SYNC
GENERATOR
SDATASCK
SL
HBLK
VGA
AD9949
PRECISION
TIMING
CORE
12-BIT
ADC
V
REF
INTERNAL
CLOCKS
PxGA
CDS
HORIZONTAL
DRIVERS
RG
H1 TO H4
HD VD
CLI
CLP/PBLK
0dB TO 18dB
03751-001
4
12
Figure 1.
AD9949* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
Data Sheet
AD9949: 12-Bit CCD Signal Processor with
Precision
Timing
™ Core Data Sheet
DESIGN RESOURCES
AD9949 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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AD9949
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Specifications..................................................................................... 3
General Specifications ................................................................. 3
Digital Specifications ................................................................... 3
Analog Specifications................................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
Equivalent Input/Output Circuits .................................................. 9
Typical Performance Characteristics ........................................... 10
System Overview ............................................................................ 11
H-Counter Behavior .................................................................. 11
Serial Interface Timing .................................................................. 12
Complete Register Listing ............................................................. 13
Precision Timing High Speed Timing Generation...................... 18
Timing Resolution...................................................................... 18
High Speed Clock Programmability........................................ 18
H-Driver and RG Outputs ........................................................ 19
Digital Data Outputs.................................................................. 19
Horizontal Clamping and Blanking............................................. 21
Individual CLPOB and PBLK Sequences................................ 21
Individual HBLK Sequences..................................................... 21
Generating Special HBLK Patterns.............................................. 23
Horizontal Sequence Control................................................... 23
External HBLK Signal................................................................ 23
H-Counter Synchronization ..................................................... 24
Power-Up Procedure...................................................................... 25
Recommended Power-Up Sequence ....................................... 25
Analog Front End Description and Operation .......................... 26
DC Restore .................................................................................. 26
Correlated Double Sampler ...................................................... 26
PxGA............................................................................................ 26
Variable Gain Amplifier ............................................................ 29
ADC ............................................................................................. 29
Optical Black Clamp .................................................................. 29
Digital Data Outputs.................................................................. 29
Applications Information .............................................................. 30
Circuit Configuration................................................................ 30
Grounding and Decoupling Recommendations.................... 30
Driving the CLI Input................................................................ 31
Horizontal Timing Sequence Example.................................... 31
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
11/04—Data Sheet Changed from Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 35
9/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Analog Specifications .................................................. 4
Changes to Terminology Section.................................................... 9
Added H-Counter Behavior Section............................................ 12
Changes to Table 7.......................................................................... 14
Changes to Table 12 ....................................................................... 17
Changes to Table 15 ....................................................................... 17
Changes to H-Counter Sync Section ........................................... 24
Changes to Recommended Power-Up Sequence Section......... 25
Changes to Ordering Guide .......................................................... 35
5/03—Revision 0: Initial Version

AD9949KCPZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit CCD Signal Processor
Lifecycle:
New from this manufacturer.
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