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AD9949KCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
AD9949
Rev. B | Page 15 of 36
Table 10. CLPOB Register Map
Address
Data Bit
Content
Default Value
(Hex)
Name Description
20 [3:0] F CLPOBPOL Start Polarities for CLPOB Sequences 0, 1, 2, and 3.
21 [23:0] FFFFFF CLPOBTOG_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
22 [23:0] FFFFFF CLPOBTOG_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
23 [23:0] FFFFFF CLPOBTOG_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
24 [23:0]
FFFFFF
0
CLPOBTOG_3
CLPOBSCP0
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
CLPOB Sequence-Change Position 0 (Hard-Coded to 0).
25 [7:0] 0 CLPOBSPTR CLPOB Sequence Pointers for Region 0 [1:0], 1 [3:2], 2[5:4], 3[7:6].
26 [11:0] FFF CLPOBSCP1 CLPOB Sequence-Change Position 1.
27 [11:0] FFF CLPOBSCP2 CLPOB Sequence-Change Position 2.
28 [11:0] FFF CLPOBSCP3 CLPOB Sequence-Change Position 3.
Table 11. PBLK Register Map
Address
Data Bit Con-
tent
Default Value
(Hex)
Name Description
30 [3:0] F PBLKPOL Start Polarities for PBLK Sequences 0, 1, 2, and 3.
31 [23:0] FFFFFF PBLKTOG_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
32 [23:0] FFFFFF PBLKTOG_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
33 [23:0] FFFFFF PBLKTOG_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
34 [23:0]
FFFFFF
0
PBLKTOG_3
PBLKSCP0
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
PBLK Sequence-Change Position 0 (Hard-Coded to 0).
35 [7:0] 0 PBLKSPTR PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
36 [11:0] FFF PBLKSCP1 PBLK Sequence-Change Position 1.
37 [11:0] FFF PBLKSCP2 PBLK Sequence-Change Position 2.
38 [11:0] FFF PBLKSCP3 PBLK Sequence-Change Position 3.
AD9949
Rev. B | Page 16 of 36
Table 12. HBLK Register Map
Address
Data Bit
Content
Default Value
(Hex)
Name Description
40 [0] 0 HBLKDIR
HBLK Internal/External.
0 = Internal.
1 = External.
41 [0] 0 HBLKPOL
HBLK External Active Polarity.
0 = Active Low.
1 = Active High.
42 [0] 1 HBLKEXTMASK
HBLK External Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1High.
43 [3:0] F HBLKMASK
HBLK Internal Masking Polarity for Each Sequence 0 to 3.
0 = Mask H1 Low.
1 = Mask H1 High.
44 [23:0] FFFFFF HBLKTOG12_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
45 [23:0] FFFFFF HBLKTOG34_0 Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
46 [23:0] FFFFFF HBLKTOG56_0 Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
47 [23:0] FFFFFF HBLKTOG12_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
48 [23:0] FFFFFF HBLKTOG34_1 Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
49 [23:0] FFFFFF HBLKTOG56_1 Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4A [23:0] FFFFFF HBLKTOG12_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4B [23:0] FFFFFF HBLKTOG34_2 Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4C [23:0] FFFFFF HBLKTOG56_2 Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
4D [23:0] FFFFFF HBLKTOG12_3 Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
4E [23:0] FFFFFF HBLKTOG34_3 Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
4F [23:0]
FFFFFF
0
HBLKTOG56_3
HBLKSCP0
Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6[23:12].
HBLK Sequence-Change Position 0 (Hard-coded to 0).
50 [7:0] 0 HBLKSPTR HBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], 3 [7:6].
51 [11:0] FFF HBLKSCP1 HBLK Sequence-Change Position 1.
52 [11:0] FFF HBLKSCP2 HBLK Sequence-Change Position 2.
53 [11:0] FFF HBLKSCP3 HBLK Sequence-Change Position 3.
Table 13. H1 to H2, RG, SHP, SHD Register Map
Address
Data Bit
Content
Default Value Name Description
60 [12:0] 01001 H1CONTROL
H1 Signal Control. Polarity [0](0 = Inversion, 1 = No Inversion).
H1 Positive Edge Location [6:1].
H1 Negative Edge Location [12:7].
61 [12:0] 00801 RGCONTROL
RG Signal Control. Polarity [0](0 = Inversion, 1 = No Inversion).
RG Positive Edge Location [6:1].
RG Negative Edge Location [12:7].
62 [14:0] 0 DRVCONTROL
Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and RG
[14:12].
Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA,
3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.
63 [11:0] 00024 SAMPCONTROL
SHP/SHD Sample Control. SHP Sampling Location [5:0]. SHD Sampling
Location [11:6].
64 [5:0] 0 DOUTPHASE DOUT Phase Control.
AD9949
Rev. B | Page 17 of 36
Table 14. AFE Operation Register Detail
Address
Data Bit
Content
Default
Value
Name Description
00 [1:0] 0 PWRDOWN
0 = Normal Operation.
1 = Reference Standby.
2/3 = Total Power-Down
[2] 1 CLPENABLE
0 = Disable OB Clamp.
1 = Enable OB Clamp.
[3] 0 CLPSPEED
0 = Select Normal OB Clamp Settling.
1 = Select Fast OB Clamp Settling.
[4] 0 FASTUPDATE
0 = Ignore VGA Update.
1 = Very Fast Clamping when VGA Is Updated.
[5] 0 PBLK_LVL
DOUT Value during PBLK.
0 = Blank to Zero.
1 = Blank to Clamp Level.
[7:6] 0 TEST MODE Test Operation Only. Set to zero.
[8] 0 DCBYP
0 = Enable DC restore circuit.
1 = Bypass DC Restore Circuit during PBLK.
[9] 0 TESTMODE Test Operation Only. Set to zero.
[11:10] 0 CDSGAIN
Adjustment of CDS Gain.
0 = 0 dB.
01 = −2 dB.
10 = −4 dB.
11 = 0 dB.
Table 15. AFE Control Register Detail
Address
Data Bit
Content
Default
Value
Name Description
03 [1:0] 0 COLORSTEER
0 = Off.
1 = Progressive.
2 = Interlaced.
3 = Three Field.
[2] 1 PxGAENABLE
0 = Disable PxGA.
1 = Enable PxGA.
[3] 0 DOUTDISABLE
0 = Data Outputs Are Driven.
1 = Data Outputs Are Three-Stated.
[4] 0 DOUTLATCH
0 = Latch Data Outputs with DOUT Phase.
1 = Output Latch Transparent.
[5] 0 GRAYENCODE
0 = Binary Encode Data Outputs.
1 = Gray Encode Data Outputs.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

AD9949KCPZRL

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Buy AD9949KCPZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit CCD Signal Processor
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