AD9949
Rev. B | Page 6 of 36
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
With
Respect to Rating
AVDD and TCVDD AVSS −0.3 V to +3.9 V
HVDD and RGVDD
HVSS,
RGVSS
−0.3 V to +3.9 V
DVDD and DRVDD
DVSS,
DRVSS
−0.3 V to +3.9 V
Any VSS Any VSS −0.3 V to +0.3 V
Digital Outputs DRVSS −0.3 V to DRVDD + 0.3 V
CLPOB/PBLK and HBLK DVSS −0.3 V to DVDD + 0.3 V
SCK, SL, and SDATA DVSS −0.3 V to DVDD + 0.3 V
RG RGVSS −0.3 V to RGVDD + 0.3 V
H1 to H4 HVSS −0.3 V to HVDD + 0.3 V
REFT, REFB, and CCDIN AVSS −0.3 V to AVDD + 0.3 V
Junction Temperature 150°C
Lead Temperature (10 s) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device
reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
40-Lead LFCSP Package: θ
JA
= 27°C/W
1
.
1
θ
JA
is measured using a 4-layer PCB with the exposed paddle soldered to the
board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
AD9949
Rev. B | Page 7 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03751-003
AD9949
TOP VIEW
1
D1
D8
D7
D6
D5
DRVDD
DRVSS
D4
D3
D2
2
3
4
5
6
7
8
9
10
RGVSS
H4
H3
HVDD
HVSS
H2
H1
(MSB) D11
D10
D9
11
12
13
14
15
16
17
18
19
20
30
REFB
RG
RGVDD
TCVSS
TCVDD
CLI
AVDD
CCDIN
AVSS
REFT
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
SL
D0 (LSB)
CLP/PBLK
HBLK
DVDD
DVSS
HD
VD
SCK
SDI
PIN 1
INDICATOR
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 to 4 D1 to D4 DO Data Outputs
5 DRVSS P Digital Driver Ground
6 DRVDD P Digital Driver Supply
7 to 13 D5 to D11 DO Data Outputs (D11 is MSB)
14 H1 DO CCD Horizontal Clock 1
15 H2 DO CCD Horizontal Clock 2
16 HVSS P H1 to H4 Driver Ground
17 HVDD P H1 to H4 Driver Supply
18 H3 DO CCD Horizontal Clock 3
19 H4 DO CCD Horizontal Clock 4
20 RGVSS P RG Driver Ground
21 RG DO CCD Reset Gate Clock
22 RGVDD P RG Driver Supply
23 TCVSS P Analog Ground for Timing Core
24 TCVDD P Analog Supply for Timing Core
25 CLI DI Master Clock Input
26 AVDD P Analog Supply for AFE
27 CCDIN AI Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor)
28 AVSS P Analog Ground for AFE
29 REFT AO Reference Top Decoupling (Decouple with 1.0 µF to AVSS)
30 REFB AO Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS)
31 SL DI 3-Wire Serial Load
32 SDI DI 3-Wire Serial Data Input
33 SCK DI 3-Wire Serial Clock
34 VD DI Vertical Sync Pulse
35 HD DI Horizontal Sync Pulse
36 DVSS P Digital Ground
37 DVDD P Digital Supply
38 HBLK DI Optional HBLK Input
39 CLP/PBLK DO CLPOB or PBLK Output
40 D0 DO Data Output LSB
1
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
AD9949
Rev. B | Page 8 of 36
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively, must
be present over all operating conditions.
Integral Nonlinearity (INL)
INL is the deviation of each individual code measured from a
true straight line from zero to full scale. The point used as zero
scale occurs 0.5 LSB before the first code transition. Positive full
scale is defined as a level 1 LSB and 0.5 LSB beyond the last
code transition. The deviation is measured from the middle of
each particular output code to the true straight line.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9949 from a straight line.
The point used as zero scale occurs 0.5 LSB before the first code
transition. Positive full scale is defined as a level 1 LSB and
0.5 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
straight line reference. The error is then expressed as a
percentage of the 2 V ADC full-scale signal. The input signal is
appropriately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be con-
verted to an equivalent voltage, using the relationship
1 LSB = (ADC full scale/2
n
codes)
where n is the bit resolution of the ADC. For the AD9949,
1 LSB is approximately 0.488 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.

AD9949KCPZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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