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AD9949KCPZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
AD9949
Rev. B | Page 3 of 36
SPECIFICATIONS
GENERAL SPECIFICATIONS
Table 1.
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating −20 +85 °C
Storage −65 +150 °C
MAXIMUM CLOCK RATE 36 MHz
POWER SUPPLY VOLTAGE
AVDD, TCVDD (AFE, Timing Core) 2.7 3.0 3.6 V
HVDD (H1 to H4 Drivers) 2.7 3.0 3.6 V
RGVDD (RG Driver) 2.7 3.0 3.6 V
DRVDD (D0 to D11 Drivers) 2.7 3.0 3.6 V
DVDD (All Other Digital) 2.7 3.0 3.6 V
POWER DISSIPATION
36 MHz, HVDD = RGVDD = 3 V, 100 pF H1 to H4 Loading
1
320 mW
Total Shutdown Mode 1 mW
1
The total power dissipated by the HVDD supply may be approximated using the equation
Total HVDD Power = (CLOAD x HVDD x Pixel Frequency) x HVDD x (Number of H – Outputs Used)
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply, reduces the power dissipation.
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, C
L
= 20 pF, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.1 V
Low Level Input Voltage V
IL
0.6 V
High Level Input Current I
IH
10 µA
Low Level Input Current I
IL
10 µA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA V
OH
2.2 V
Low Level Output Voltage, I
OL
= 2 mA V
OL
0.5 V
CLI INPUT
High Level Input Voltage
(TCVDD/2 + 0.5 V) V
IH–CLI
1.85 V
Low Level Input Voltage V
IL–CLI
0.85 V
RG AND H-DRIVER OUTPUTS
High Level Output Voltage
(RGVDD – 0.5 V and HVDD – 0.5 V) V
OH
2.2 V
Low Level Output Voltage V
OL
0.5 V
Maximum Output Current (Programmable) 30 mA
Maximum Load Capacitance 100 pF
AD9949
Rev. B | Page 4 of 36
ANALOG SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
CLI
= 36 MHz, typical timing specifications, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Notes
CDS
Gain 0 dB
Allowable CCD Reset Transient
1
500 mV
Maximum Input Range before Saturation
1
1.0 V p-p
Maximum CCD Black Pixel Amplitude
1
±50 mV
PIXEL GAIN AMPLIFIER (P×GA)
Gain Control Resolution 256 Steps
Gain Monotonicity
Minimum Gain 0 dB
Maximum Gain 18 dB
VARIABLE GAIN AMPLIFIER (VGA)
Maximum Input Range 1.0 V p-p
Maximum Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Minimum Gain (VGA Code 0) 6 dB
Maximum Gain (VGA Code 1023) 42 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC output
Minimum Clamp Level (0) 0 LSB
Maximum Clamp Level (255) 255 LSB
A/D CONVERTER
Resolution 12 Bits
Differential Nonlinearity (DNL) −1.0 ±0.5 +1.0 LSB
No Missing Codes Guaranteed
Integral Nonlinearity (INL) 8 LSB
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications include entire signal chain
VGA Gain Accuracy
Minimum Gain (Code 0) 5.0 5.5 6.0 dB
Maximum Gain (Code 1023) 40.5 41.5 42.5 dB
Peak Nonlinearity, 500 mV Input Signal 0.15 0.6 % 12 dB gain applied
Total Output Noise 0.8 LSB rms AC grounded input, 6 dB gain applied
Power Supply Rejection (PSR) 50 dB Measured with step change on supply
1
Input signal characteristics defined as follows:
50mV MAX
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V MAX
INPUT SIGNAL RANGE
03751-002
AD9949
Rev. B | Page 5 of 36
TIMING SPECIFICATIONS
C
L
= 20 pF, f
CLI
= 36 MHz, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit
MASTER CLOCK (CLI) (See Figure 16)
CLI Clock Period t
CLI
27.8 ns
CLI High/Low Pulse Width t
ADC
11.2 13.9 16.6 ns
Delay from CLI to Internal Pixel Period Position t
CLIDLY
6 ns
CLPOB PULSE WIDTH (PROGRAMMABLE)
1
t
COB
2 20 Pixels
SAMPLE CLOCKS (See Figure 18)
SHP Rising Edge to SHD Rising Edge t
S1
12.5 13.9 ns
DATA OUTPUTS (See Figure 19 and Figure 20)
Output Delay From Programmed Edge t
OD
6 ns
Pipeline Delay 11 Cycles
SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15)
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
SCK Falling Edge to SDATA Valid Read t
DV
10 ns
1
Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
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AD9949KCPZRL

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Buy AD9949KCPZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit CCD Signal Processor
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