OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LT3957EUHE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LT3957
10
3957f
APPLICATIONS INFORMATION
INTV
CC
Regulator Bypassing and Operation
An internal, low dropout (LDO) voltage regulator produces
the 5.2V INTV
CC
supply which powers the gate driver, as
shown in Figure 1. The LT3957 contains an undervoltage
lockout comparator A8 for the INTV
CC
supply. The INTV
CC
undervoltage (UV) threshold is 2.7V (typical), with 0.1V
hysteresis, to ensure that the internal MOSFET has suf-
fi cient gate drive voltage before turning on. When INTV
CC
is below the UV threshold, the internal power switch will
be turned off and the soft-start operation will be triggered.
The logic circuitry within the LT3957 is also powered from
the internal INTV
CC
supply.
The INTV
CC
regulator must be bypassed to SGND imme-
diately adjacent to the IC pins with a minimum of 4.7µF
ceramic capacitor. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
driver.
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the internal power
MOSFET. The on-chip power dissipation can be signifi cant
when the internal power MOSFET is being driven at a high
frequency and the V
IN
voltage is high.
An effective approach to reduce the power consumption of
the internal LDO for gate drive and to improve the effi ciency
is to tie the INTV
CC
pin to an external voltage source high
enough to turn off the internal LDO regulator.
In SEPIC or fl yback applications, the INTV
CC
pin can be
connected to the output voltage V
OUT
through a blocking
diode, as shown in Figure 2, if V
OUT
meets the following
conditions:
1. V
OUT
< V
IN
(pin voltage)
2. V
OUT
< 8V
A resistor R
VCC
can be connected, as shown in Figure 2, to
limit the inrush current from V
OUT
. Regardless of whether
or not the INTV
CC
pin is connected to an external voltage
source, it is always necessary to have the driver circuitry
bypassed with a 4.7µF low ESR ceramic capacitor to ground
immediately adjacent to the INTV
CC
and SGND pins.
If LT3957 operates at a low V
IN
and high switching fre-
quency, the voltage drop across the drain and the source of
the LDO PMOS (M2 in Figure 1) could push INTV
CC
to be
below the UV threshold. To prevent this from happening,
the INTV
CC
pin can be shorted directly to the V
IN
pin. V
IN
must not exceed the INTV
CC
Absolute Maximum Rating
(8V). In this condition, the internal LDO will be turned off
and the gate driver will be powered directly from V
IN
. It is
recommended that INTV
CC
pin be shorted to the V
IN
pin if
V
IN
is lower than 3.5V at 1MHz switching frequency, or V
IN
is lower than 3.2V at 100kHz switching frequency. With
the INTV
CC
pin shorted to V
IN
, however, a small current
(around 16µA) will load the INTV
CC
in shutdown mode.
Figure 2. Connecting INTV
CC
to V
OUT
C
VCC
4.7µF
V
OUT
3957 F02
INTV
CC
SGND
LT3957
R
VCC
D
VCC
LT3957
11
3957f
APPLICATIONS INFORMATION
Operating Frequency and Synchronization
The choice of operating frequency may be determined by
on-chip power dissipation (a low switching frequency may
be required to ensure IC junction temperature does not
exceed 125°C), otherwise it is a trade-off between effi ciency
and component size. Low frequency operation improves
effi ciency by reducing gate drive current and MOSFET
and diode switching losses. However, lower frequency
operation requires a physically larger inductor. Switching
frequency also has implications for loop compensation.
The LT3957 uses a constant-frequency architecture that
can be programmed over a 100kHz to 1000kHz range
with a single external resistor from the RT pin to SGND,
as shown in Figure 1. A table for selecting the value of R
T
for a given operating frequency is shown in Table 1.
Table 1. Timing Resistor (R
T
) Value
SWITCHING FREQUENCY (kHz) R
T
(kΩ)
100 140
200 63.4
300 41.2
400 30.9
500 24.3
600 19.6
700 16.5
800 14
900 12.1
1000 10.5
The operating frequency of the LT3957 can be synchronized
to an external clock source. By providing a digital clock
signal into the SYNC pin, the LT3957 will operate at the
SYNC clock frequency. The LT3957 detects the rising edge
of each clock cycle. If this feature is used, an R
T
resistor
should be chosen to program a switching frequency 20%
slower than SYNC pulse frequency. It is recommended that
the SYNC pin has a minimum pulse width of 200ns. Tie
the SYNC pin to SGND if this feature is not used.
Duty Cycle Consideration
Switching duty cycle is a key variable defi ning con-
verter operation. As such, its limits must be considered.
Minimum on-time is the smallest time duration that the
LT3957 is capable of turning on the power MOSFET. This
time is typically about 240ns (see Minimum On-Time in
the Electrical Characteristics table). In each switching
cycle, the LT3957 keeps the power switch off for at least
220ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
The minimum on-time, minimum off-time and the switching
frequency defi ne the minimum and maximum switching
duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
The output voltage V
OUT
is set by a resistor divider, as
shown in Figure 1. The positive and negative V
OUT
are set
by the following equations:
V
OUT,POSITIVE
=1.6V • 1+
R2
R1
⎛
⎝
⎜
⎞
⎠
⎟
V
OUT,NEGATIVE
= –0.8V • 1+
R2
R1
⎛
⎝
⎜
⎞
⎠
⎟
The resistors R1 and R2 are typically chosen so that
the error caused by the current fl owing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
LT3957
12
3957f
APPLICATIONS INFORMATION
Soft-Start
The LT3957 contains several features to limit peak switch
currents and output voltage (V
OUT
) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since V
OUT
is far from its fi nal value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The LT3957 addresses this mechanism with the SS pin.
As shown in Figure 1, the SS pin reduces the power
MOSFET current by pulling down the VC pin through
Q2. In this way the SS allows the output capacitor to
charge gradually toward its fi nal value while limiting the
start-up peak currents. The typical start-up waveforms
are shown in the Typical Performance Characteristics
section. The inductor current I
L
slewing rate is limited by
the soft-start function.
Besides start-up (with EN/UVLO), soft-start can also be
triggered by the following faults:
1. INTV
CC
< 2.85V
2. Thermal lockout (TLO > 165°C)
Any of these three faults will cause the LT3957 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10µA current source I
S2
starts
charging the SS pin, initiating a soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
T
SS
=C
SS
•
1.25V
10µA
FBX Frequency Foldback
When V
OUT
is very low during start-up, or an output short-
circuit on a SEPIC, an inverting, or a fl yback converter, the
switching regulator must operate at low duty cycles to keep
the power switch current below the current limit, since
the inductor current decay rate is very low during switch
off time. The minimum on-time limitation may prevent the
switcher from attaining a suffi ciently low duty cycle at the
programmed switching frequency. So, the switch current
may keep increasing through each switch cycle, exceed-
ing the programmed current limit. To prevent the switch
peak currents from exceeding the programmed value, the
LT3957 contains a frequency foldback function to reduce
the switching frequency when the FBX voltage is low (see
the Normalized Switching Frequency vs FBX graph in the
Typical Performance Characteristics section).
During frequency foldback, external clock synchroniza-
tion is disabled to prevent interference with frequency
reducing operation.
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3957 uses current mode control to
regulate the output which simplifi es loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3957, a series resistor-capacitor
network is usually connected from the VC pin to SGND.
Figure 1 shows the typical VC compensation network.
For most applications, the capacitor should be in the
range of 470pF to 22nF, and the resistor should be in the
range of 5k to 50k. A small capacitor is often connected
in parallel with the RC compensation network to attenu-
ate the VC voltage ripple induced from the output voltage
ripple through the internal error amplifi er. The parallel
capacitor usually ranges in value from 10pF to 100pF. A
practical approach to design the compensation network
is to start with one of the circuits in this data sheet that
is similar to your application, and tune the compensation
network to optimize the performance. Stability should
then be checked across all operating conditions, including
load current, input voltage and temperature. Application
Note 76 is a good reference on loop compensation.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

LT3957EUHE#PBF

Mfr. #:
Buy LT3957EUHE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Input Voltage, Boost, flyback, SEPIC and Inverting Converter
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet