LTC2943
13
2943fa
For more information www.linear.com/LTC2943
Alert Thresholds Registers (E,F,G,H,K,L,M,N,Q,R,S,
T,W,X)
For
each of the measured quantities (battery charge,
voltage, current and temperature) the LTC2943 features
high and low threshold registers. At power-up, the high
thresholds are set to FFFFh while the low thresholds are set
to 0000h, with the effect of disabling them. All thresholds
can be programmed to a desired value via I
2
C. As soon
as a measured quantity exceeds the high threshold or
falls below the low threshold, the LTC2943 sets the cor
-
responding flag in the status register and pulls the ALCC
pin low if alert mode is enabled via bits B[2:1].
Accumulated Charge Register (C,D)
The coulomb counting circuitry in the LTC2943 integrates
current through the sense resistor. The result of this charge
integration is stored in the 16-bit accumulated charge
register (registers C, D). As the LTC2943 does not know
the actual battery status at power-up, the accumulated
charge register (ACR) is set to mid-scale (7FFFh). If the
host knows the status of the battery, the accumulated
charge (C[7:0]D[7:0]) can be either programmed to the
correct value via I
2
C or it can be set after charging to FFFFh
(full) by pulling the ALCC pin low if charge complete mode
is enabled via bits B[2:1]. Note that before writing to the
accumulated charge registers, the analog section should
be temporarily shut down by setting B[0] to 1. In order to
avoid a change in the accumulated charge registers between
reading MSBs C[7:0] and LSBs D[7:0], it is recommended
to read them sequentially as shown in Figure 10.
Voltage Registers (I,J), and Voltage Threshold
Registers (K,L,M,N)
The result of the 14-bit ADC conversion of the voltage at
SENSE
is stored in the voltage registers (I, J).
From the result of the 16-bit voltage registers I[7:0]J[7:0]
the measured voltage can be calculated as:
V
SENSE
=23.6V
RESULT
h
FFFF
h
=23.6V
RESULT
DEC
65535
Example 1: a register value I[7:0] = B0h and J[7:0] = 1Ch
corresponds to a voltage on SENSE
of:
V
SENSE
=23.6V
B01C
h
FFFF
h
=23.6V
45084
DEC
65535
16.235V
Example 2: To set a low level threshold for the battery
voltage of 7.2V, register M should be programmed to 4Eh
and register N to 1Ah.
Current Registers (O,P) and Current Threshold
Registers (Q,R,S,T)
The result of the current conversion is stored in the cur
-
rent registers (O,P).
As
the ADC resolution is 12 bits in current mode, the
lowest four bits of the combined current registers (O, P)
are always zero.
The ADC measures battery current by converting the volt
-
age, V
SENSE
, across the sense resistor R
SENSE
. Depending
on whether the battery is being charged or discharged, the
measured voltage drop on R
SENSE
is positive or negative.
The result is stored in registers O and P in excess –32767
representation. O[7:0] = FFh, P[7:0] = FFh corresponds to
the full scale positive voltage 60mV. While O[7:0] = 00h,
P[7:0] = 00h corresponds to the full scale negative volt
-
age –60mV. The
battery current can be obtained from the
two byte register O[7:0]P[7:0] and the value of the chosen
sense resistor R
SENSE
:
I
BAT
=
V
SENSE
R
SENSE
=
60mV
R
SENSE
RESULT
h
7FFF
h
7FFF
h
=
60mV
R
SENSE
RESULT
DEC
32767
32767
Positive current is measured when the battery is charg-
ing and negative current is measured when the battery is
discharging.
APPLICATIONS INFORMATION
LTC2943
14
2943fa
For more information www.linear.com/LTC2943
Example 1: a register value of O[7:0] = A8h P[7:0] = 40h
together with a sense resistor R
SENSE
= 50mΩ corresponds
to a battery current:
I
BAT
=
60mV
50m
A840
h
7FFF
h
7FFF
h
=
60mV
50m
4307232767
32767
377.3mA
The positive current result indicates that the battery is
being charged.
The values in the threshold register for the current mode
Q,R,S,T are also expressed in excess –32767 representa
-
tion in the same manner as the current conversion result.
The
alert after a current measurement is set if the result
is higher than the value stored in the high threshold reg
-
isters Q,R or lower than the value stored in the low value
registers S,T.
Example 2: In an application, the user wants to get an
alert if the absolute current through the sense resistor,
R
SENSE
, of 50exceeds 1A. This is achieved by setting
the upper threshold I
HIGH
in register [Q,R] to 1A and the
lower threshold I
LOW
in register [S,T] to –1A. The formula
for I
BAT
leads to:
I
HIGH(DEC)
=
1A 50mΩ
60mV
32767 +32767= 60073
I
LOW (DEC)
=
–1A 50mΩ
60mV
32767 + 32767= 5461
Leading the user to set Q[7:0] = EAh, R[7:0] = A9h for
the high threshold and S[7:0] = 15h and T[7:0] = 55h for
the low threshold.
Temperature Registers (U,V), and Temperature
Threshold Registers (W,X)
As the ADC resolution is 11 bits in temperature mode, the
lowest five bits of the combined temperature registers
(U, V) are always zero.
The
actual temperature can be obtained from the two byte
register U[7:0]V[7:0] by:
T =510K
RESULT
h
FFFF
h
=510K
RESULT
DEC
65535
Example: a register value of U[7:0] = 96h, V[7:0] = 96h
corresponds to ~300K or ~27°C
A high temperature limit of 60°C is programmed by setting
register W to A7h. Note that the temperature threshold
register is a single byte register and only the eight MSBs
of the 11 bits temperature result are checked.
Effect of Differential Offset Voltage on Total Charge
Error
In battery gas gauges, an important parameter is the
differential offset (V
OS
) of the circuitry monitoring the
battery charge. Many coulomb counter devices perform
an analog to digital conversion of V
SENSE
, where V
SENSE
is the voltage drop across the sense resistor, and ac-
cumulate the
conversion results to infer charge. In such
an architecture, the differential offset V
OS
causes relative
charge error of V
OS
/V
SENSE
. For small V
SENSE
values V
OS
can be the main source of error.
The LTC2943 performs the tracking of the charge with an
analog integrator. This approach allows to continuously
monitor the battery charge and significantly lowers the
error due to differential offset. The relative charge error
due to offset (CE
OV
) can be expressed by:
CE
OV
=
V
OS
V
SENSE
2
As example, at a 1mV input signal, a differential voltage
offset V
OS
= 20µV results in a 2% error using digital
integration, whereas the error is only 0.04% (a factor of
50 times smaller!) using the analog integration approach
of LTC2943.
APPLICATIONS INFORMATION
LTC2943
15
2943fa
For more information www.linear.com/LTC2943
The reduction of the impact of the offset in LTC2943 can
be explained by its integration scheme depicted in Figure 2.
While positive
offset accelerates the up ramping of the
integrator output from REFLO to REFHI, it slows the down
ramping from REFHI to REFLO thus the effect is largely
canceled as depicted below.
I
2
C Protocol
The LTC2943 uses an I
2
C/SMBus-compatible 2-wire
interface supporting multiple devices on a single bus.
Connected devices can only pull the bus lines low and
must never drive the bus high. The bus wires are externally
connected to a positive supply voltage via current sources
or
pull-up resistors. When the bus is idle, all bus lines are
high. Data on the I
2
C bus can be transferred at rates of
up to 100kbit/s in standard mode and up to 400kbit/s in
fast mode.
Each device on the I
2
C/SMbus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be classified as masters or slaves when perform
-
ing data
transfers. A master is the device which initiates a
data
transfer on the bus and generates the clock signals to
permit that transfer. At the same time any device addressed
is considered a slave. The LTC2943 always acts as a slave.
Figure 4 shows an overview of the data transmission on
the I
2
C bus.
Start and Stop Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from high to low
while SCL is high. When the master has finished com
-
municating with the slave, it issues a STOP condition by
APPLICATIONS INFORMATION
Figure 4. Data Transfer Over I
2
C or SMBus
For input signals with an absolute value smaller than the
offset of the internal op amp, the LTC2943 stops integrat-
ing and does not integrate its own offset.
I
2
C/SMBus Interface
The LTC2943 communicates with a bus master using
a 2-wire interface compatible with I
2
C and SMBus. The
7-bit hard coded I
2
C address of the LTC2943 is 1100100.
The LTC2943 is a slave only device. The serial clock line
(SCL) is input only while the serial data line (
SDA) is
bidirectional.
The device supports I
2
C standard and fast
mode. For more details refer to the I
2
C Protocol section.
2943 F0B
INTEGRATOR
OUTPUT
REFHI
REFLO
TIME
WITH OFFSET
WITHOUT OFFSET
FASTER
UP RAMPING
SLOWER
DOWN RAMPING
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS R/W ACK DATA ACK DATA ACK
1 - 7 8 9
2943 F04
a6 - a0 b7 - b0 b7 - b0
1 - 7 8 9 1 - 7 8 9
P
S

LTC2943IDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management 20V Battery Gas Gauge with Voltage, Current & Temperature Measurement
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet