NB3H60113G00MTR2G Datasheet NB3H60113G00MTR2G | P1-P3

January, 2016 − Rev. 2

1 Publication Order Number:

NB3H60113G/D

NB3H60113G

3.3 V / 2.5 V Programmable

OmniClock Generator

with Single Ended (LVCMOS/LVTTL) and

Differential (LVPECL/LVDS/ HCSL/CML)

Outputs

The NB3H60113G, which is a member of the OmniClock family, is

a one−time programmable (OTP), low power PLL−based clock

generator that supports any output frequency from 8 kHz to 200 MHz.

The device accepts fundamental mode parallel resonant crystal or a

single ended (LVCMOS/LVTTL) reference clock as input. It

generates either three single ended (LVCMOS/LVTTL) outputs, or

one single ended output and one differential

(LVPECL/LVDS/HCSL/CML) output. The output signals can be

modulated using the spread spectrum feature of the PLL

(programmable spread spectrum type, deviation and rate) for

applications demanding low electromagnetic interference (EMI).

Using the PLL bypass mode, it is possible to get a copy of the input

clock on any or all of the outputs. The device can be powered down

using the Power Down pin (PD#). It is possible to program the internal

input crystal load capacitance and the output drive current provided by

the device. The device also has automatic gain control (crystal power

limiting) circuitry which avoids the device overdriving the external

crystal.

Features

• Member of the OmniClock Family of Programmable Clock

Generators

• Operating Power Supply: 3.3 V ± 10%, 2.5 V ± 10%

• I/O Standards

♦ Inputs: LVCMOS/LVTTL, Fundamental Mode

Crystal

♦ Outputs: LVCMOS/LVTTL

♦ Outputs: LVPECL, LVDS, CML and HCSL

• 3 Programmable Single Ended (LVCMOS/LVTTL)

Outputs from 8 kHz to 200 MHz

• 1 Programmable Differential Clock Output up to

200 MHz

• Input Frequency Range

♦ Crystal: 3 MHz to 50 MHz

♦ Reference Clock: 3 MHz to 200 MHz

• Configurable Spread Spectrum Frequency Modulation

Parameters (Type, Deviation, Rate)

• Programmable Internal Crystal Load Capacitors

• Programmable Output Drive Current for Single Ended

Outputs

• Power Saving mode through Power Down Pin

• Programmable PLL Bypass Mode

• Programmable Output Inversion

• Programming and Evaluation Kit for Field

Programming and Quick Evaluation

• Temperature Range −40°C to 85°C

• Packaged in 8−Pin WDFN

• These are Pb−Free Devices

Typical Applications

• eBooks and Media Players

• Smart Wearables, Portable Medical and Industrial

Equipment

• Set Top Boxes, Printers, Digital Cameras and

Camcorders

www.onsemi.com

WDFN8

CASE 511AT

MARKING DIAGRAM

See detailed ordering and shipping information on page 21 o

this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

H0 = Specific Device Code

M = Date Code

G = Pb−Free Device

H0MG

NB3H60113G

www.onsemi.com

BLOCK DIAGRAM

Clock Buffer/

Crystal

Oscillator and

Phase

Detector

Charge

Pump

VCO

CMOS /

Diff

buffer

CMOS/

Diff

buffer

Feedback

Divider

XIN/CLKIN

XOUT

Crystal

CLK1

CLK2

CLK0

VDD

GND

Output

Divider

Output

Divider

Output

Divider

Configuration

Memory

PLL Block

Frequency

and SS

PD#

Output control

Crystal/Clock Control

PLL Bypass Mode

Figure 1. Simplified Block Diagram

AGC

CMOS

buffer

Notes:

1. CLK0 and CLK1 can be configured to be one of LVPECL, LVDS, HCSL or CML output, or two single−ended LVCMOS/ LVTTL outputs.

2. Dotted lines are the programmable control signals to internal IC blocks.

3. PD# has internal pull down resistor.

PIN FUNCTION DESCRIPTION

NB3H60113G

XIN/CLKIN

XOUT

PD#

GND

CLK0

CLK1

VDD

CLK2

Figure 2. Pin Connections (Top View) – WDFN8

NB3H60113G

www.onsemi.com

Table 1. PIN DESCRIPTION

Pin No. Pin Name Pin Type Description

1 XIN/CLKIN Input 3 MHz to 50 MHz crystal input connection or an external single−ended reference input

clock between 3 MHz and 200 MHz

2 XOUT Output Crystal output. Float this pin when external reference clock is connected at XIN

3 PD# Input Asynchronous LVCMOS/ LVTTL input. Active Low Master Reset to disable the device and

set outputs Low. Internal pull−down resistor. This pin needs to be pulled High for normal

operation of the chip.

4 GND Ground Power supply ground

5 CLK0 SE/DIFF

output

Supports 8 kHz to 200 MHz Single−Ended (LVCMOS/LVTTL) signals or Differential

(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also be a

copy of the input clock. The single ended output will be LOW and differential outputs will

be complementary LOW/HIGH until the PLL has locked and the frequency has stabilized.

6 CLK1 SE/DIFF

output

Supports 8 kHz to 200 MHz Single−Ended (LVCMOS/LVTTL) signals or Differential

(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also be a

copy of the input clock. The single ended output will be LOW and differential outputs will

be complementary LOW/HIGH until the PLL has locked and the frequency has stabilized.

7 VDD Power 3.3 V / 2.5 V power supply

8 CLK2 SE

output

Supports 8 kHz to 200 MHz Single−Ended (LVCMOS/LVTTL) signals. Using PLL Bypass

mode, the output can also be a copy of the input clock. The output will be LOW until the

PLL has locked and the frequency has stabilized.

Table 2. POWER DOWN FUNCTION TABLE

PD# Function

0 Device Powered Down

1 Device Powered Up

TYPICAL CRYSTAL PARAMETERS

Crystal: Fundamental Mode Parallel Resonant

Frequency: 3 MHz to 50 MHz

Table 3. MAX CRYSTAL LOAD CAPACITORS

RECOMMENDATION

Crystal Frequency Range Max Cap Value

3 MHz – 30 MHz 20 pF

30 MHz – 50 MHz 10 pF

Shunt Capacitance (C0): 7 pF (Max)

Equivalent Series Resistance (ESR): 150 W (Max)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

NB3H60113G00MTR2G

Mfr. #:

Buy NB3H60113G00MTR2G

Manufacturer:

ON Semiconductor

Description:

Clock Generators & Support Products 3.3 V/2.5 V OmniCloc LVCMOS/LVTTL LVPECL

Lifecycle:

New from this manufacturer.

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