NB3H60113G00MTR2G Datasheet NB3H60113G00MTR2G | P4-P6

NB3H60113G

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FUNCTIONAL DESCRIPTION

The NB3H60113G is a 3.3 V / 2.5 V programmable, single

ended / differential clock generator, designed to meet the

clock requirements for consumer and portable markets. It

has a small package size and it requires low power during

operation and while in standby. This device provides the

ability to configure a number of parameters as detailed in the

following section. The One−Time Programmable memory

allows programming and storing of one configuration in the

memory space.

NB3H60113G

XIN/CLKIN

XOUT

CLK2

CLK1

CLK0

Differential Clock

Single Ended Clock

Crystal or

Reference

Clock input

PD#

LVPECL/LVDS/

HCSL/CML

VDD

GND

3.3V/2.5V

Single Ended Clocks

R (optional)

0.1 mF

Figure 3. Power Supply Noise Suppression

0.01 mF

Power Supply

Device Supply

The NB3H60113G is designed to work with a 3.3 V/2.5 V

VDD power supply. For VDD operation of 1.8 V, refer to

NB3V60113G datasheet. In order to suppress power supply

noise it is recommended to connect decoupling capacitors of

0.1 mF and 0.01 mF close to the VDD pin as shown in

Figure 3.

Clock Input

Input Frequency

The clock input block can be programmed to use a

fundamental mode crystal from 3 MHz to 50 MHz or a

single ended reference clock source from 3 MHz to

200 MHz. When using output frequency modulation for

EMI reduction, for optimal performance, it is recommended

to use crystals with frequency more than 6.75 MHz as input.

Crystals with ESR values of up to 150 W are supported.

When using a crystal input, it is important to set crystal load

capacitor values correctly to achieve good performance.

Programmable Crystal Load Capacitors

The provision of internal programmable crystal load

capacitors eliminates the necessity of external load

capacitors for standard crystals. The internal load capacitor

can be programmed to any value between 4.36 pF and

20.39 pF with a step size of 0.05 pF. Refer to Table 3 for

recommended maximum load capacitor values for stable

operation. There are three modes of loading the crystal –

with internal chip capacitors only, with external capacitors

only or with the both internal and external capacitors. Check

with the crystal vendor’s load capacitance specification for

setting of the internal load capacitors. The minimum value

of 4.36 pF internal load capacitor need to be considered

while selecting external capacitor value. These will be

bypassed when using an external reference clock.

Automatic Gain Control (AGC)

The Automatic Gain Control (AGC) feature adjusts the

gain to the input clock based on its signal strength to

maintain a good quality input clock signal level. This feature

takes care of low clock swings fed from external reference

clocks and ensures proper device operation. It also enables

maximum compatibility with crystals from different

manufacturers, processes, quality and performance. AGC

also takes care of the power dissipation in the crystal; avoids

over driving the crystal and thus extending the crystal life.

In order to calculate the AGC gain accurately and avoid

increasing the jitter on the output clocks, the user needs to

provide crystal load capacitance as well as other crystal

parameters like ESR and shunt capacitance (C0).

NB3H60113G

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Programmable Clock Outputs

Output Type and Frequency

The NB3H60113G provides three independent single

ended LVCMOS/LVTTL outputs, or one single ended

LVCMOS/LVTTL output and one LVPECL/LVDS/HCSL/

CML differential output. The device supports any single

ended output or differential output frequency from 8 kHz up

to 200 MHz with or without frequency modulation. It should

be noted that certain combinations of output frequencies and

spread spectrum configurations may not be recommended

for optimal and stable operation.

For differential clocking, CLK0 and CLK1 can be

configured as LVPECL, LVDS, HCSL or CML. Refer to the

Application Schematic in Figure 4.

NB3H60113G

XIN / CLKIN

XOUT

VDD

3.3V / 2.5V

CLK2

CLK1

CLK0

Differential Clock

LVPECL/LVDS/HCSL/CML

Single Ended Clock

Crystal or

Reference

Clock Input

PD#

GND

Figure 4. Application Setup for Differential Output Configuration

VDD

0.01 mF0.1 mF

Programmable Output Drive

The drive strength or output current of each of the

LVCMOS clock outputs is programmable. For V

of 3.3 V

and 2.5 V four distinct levels of LVCMOS output drive

strengths can be selected as mentioned in the DC Electrical

Characteristics. This feature provides further load drive and

signal conditioning as per the application requirement.

PLL BYPASS Mode

PLL Bypass mode can be used to buffer the input clock on

any of the outputs or all of the outputs. Any of the clock

outputs can be programmed to generate a copy of the input

clock.

Output Inversion

All output clocks of the NB3H60113G can be

phase inverted relative to each other. This feature can also be

used in conjunction with the PLL Bypass mode.

Spread Spectrum Frequency Modulation

Spread spectrum is a technique using frequency

modulation to achieve lower peak electromagnetic

interference (EMI). It is an elegant solution compared to

techniques of filtering and shielding. The NB3H60113G

modulates the output of its PLL in order to “spread” the

bandwidth of the synthesized clock, decreasing the peak

amplitude at the center frequency and at the frequency’s

harmonics. This results in significantly lower system EMI

compared to the typical narrow band signal produced by

oscillators and most clock generators. Lowering EMI by

increasing a signal’s bandwidth is called ‘spread spectrum

modulation’.

NB3H60113G

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Figure 5. Frequency Modulation or Spread Spectrum Clock for EMI Reduction

The outputs of the NB3H60113G can be programmed to

have either center spread from ±0.125% to ±3% or down

spread from −0.25% to −4%. The programmable step size

for spread spectrum deviation is 0.125% for center spread

and 0.25% for down spread respectively. Additionally, the

frequency modulation rate is also programmable.

Frequency modulation from 30 kHz to 130 kHz can be

selected. Spread spectrum, when on, applies to all the

outputs of the device but not to output clocks that use the

PLL bypass feature. There exists a tradeoff between the

input clock frequency and the desired spread spectrum

profile. For certain combinations of input frequency and

modulation rate, the device operation could be unstable and

should be avoided. For spread spectrum applications, the

following limits are recommended:

Fin (Min) = 6.75 MHz

Fmod (range) = 30 kHz to 130 kHz

Fmod (Max) = Fin / 225

For any input frequency selected, above limits must be

observed for a good spread spectrum profile.

For example, the minimum recommended reference

frequency for a modulation rate of 30 kHz would be 30 kHz

* 225 = 6.75 MHz. For 27 MHz, the maximum recommended

modulation rate would be 27 MHz / 225 = 120 kHz.

Control Inputs

Power Down

Power saving mode can be activated through the power

down PD# input pin. This input is an LVCMOS/LVTTL

active Low Master Reset that disables the device and sets

outputs Low. By default it has an internal pull−down resistor.

The chip functions are disabled by default and when PD# pin

is pulled high the chip functions are activated.

Configuration Space

NB3H60113G has one Configuration. Table 4 shows an

example of device configuration.

Table 4. EXAMPLE CONFIGURATION

Input

Frequency

Output Frequency VDD SS%

SS Mod

Rate

Output Drive

Output

Inversion

Output

Enable

PLL Bypass Notes

24 MHz CLK0 = 33 MHz

CLK1 = 12 MHz

CLK2 = 24 MHz

3.3 V −0.5% 100 kHz CLK0 = 12 mA

CLK1 = 8 mA

CLK2 = 4 mA

CLK0 = N

CLK1 = N

CLK2 = Y

CLK0 = Y

CLK1 = Y

CLK2 = Y

CLK0 = N

CLK1 = N

CLK2 = Y

CLK2 Ref clk

Default Device State

The NB3H60113G parts shipped from ON Semiconductor

are blank, with no inputs/outputs programmed. These need

to be programmed by the field sales or distribution or by the

user themselves before they can be used. Programmable

clock software downloadable from the ON Semiconductor

website can be used along with the programming kit to

achieve this purpose. For mass production, parts can be

programmed with a customer qualified configuration and

sourced from ON Semiconductor as a dash part number (Eg.

NB3H60113G−01).

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NB3H60113G00MTR2G

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Manufacturer:

ON Semiconductor

Description:

Clock Generators & Support Products 3.3 V/2.5 V OmniCloc LVCMOS/LVTTL LVPECL

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New from this manufacturer.

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