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831724AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
1©2016 Integrated Device Technology, Inc Revision B November 16, 2016
General Description
The 831724 is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing and fanout of high-frequency clock and data signals.
The device has two differential, selectable clock/data inputs. The
selected input signal is distributed to four low-skew differential HCSL
outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.
The 831724 is characterized to operate from a 3.3V power supply.
Guaranteed input, output-to-output and part-to-part skew
characteristics make the 831724 ideal for those clock and data
distribution applications demanding well-defined performance and
repeatability. The 831724 supports the clock multiplexing and
distribution of PCI Express Generation 1, 2, and 3 clock signals.
Features
• 2:1 differential clock/data multiplexer with fanout
• Two selectable, differential inputs
• Each differential input pair can accept the following levels: HCSL,
LVDS, LVPECL.
• Four differential HCSL outputs
• Maximum input/output clock frequency: 350MHz
• Maximum input/output data rate: 700Mb/s (NRZ)
• LVCMOS interface levels for all control inputs
• PCI Express Gen 1,2,3 jitter compliant
• Input skew: 165ps (maximum)
• Output skew: 175ps (maximum)
• Part-to-part skew: 450ps (maximum)
• Full 3.3V supply voltage
• Available in lead-free (RoHS 6) package
• -40°C to 85°C ambient operating temperature
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDD
nOED
CLK0
nCLK0
CLK1
nCLK1
nOEA
V
DD
nc
nOEC
nc
nc
nc
nc
SEL
nc
VDD
QA
nQA
GND
QB
nQB
V
DD
nOEB
nQD
QD
GND
nQC
QC
V
DD
IREF
V
DD
Block Diagram
QA
nQA
QB
nQB
QC
nQC
QD
nQD
IREF
CLK0
nCLK0
CLK1
nCLK1
SEL
Pulldown
Pullup
Pullup
Pullup
Pullup
Pullup/down
Pulldown
Pullup/down
Pulldown
0
1
Pin Assignment
831724I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
831724
Datasheet
Differential Clock/Data Multiplexer
2©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 8, 9, 15,
26, 32
V
DD
Power
Positive power supply pins.
2 nOED Input Pullup
Output enable for the QD output. See Table 3D for function. LVCMOS/LVTTL
interface levels.
3 CLK0 Input Pulldown
Non-inverting clock/data input 0.
4 nCLK0 Input Pulldown/Pullup
Inverting differential clock input 0. V
DD
/2 default when left floating.
5 CLK1 Input Pulldown
Non-inverting clock/data input 1.
6 nCLK1 Input Pulldown/Pullup
Inverting differential clock input 1. V
DD
/2 default when left floating.
7 nOEA Input Pullup
Output enable for the QA output. See Table 3A for function. LVCMOS/LVTTL
interface levels.
10, 11 QA, nQA Output
Differential output pair A. HCSL interface levels.
12, 29 GND Power
Power supply ground.
13, 14 QB, nQB Output
Differential output pair B. HCSL interface levels.
16 nOEB Input Pullup
Output enable for the QB output. See Table 3B for function. LVCMOS/LVTTL
interface levels.
17, 19, 20,
21, 22, 24
nc Unused
No connect pins.
18 SEL Input Pulldown
Input select. See Table 3E for function.
LVCMOS/LVTTL interface levels.
23 nOEC Input Pullup
Output enable for the QC output. See Table 3C for function. LVCMOS/LVTTL
interface levels.
25 IREF Input
An external fixed precision resistor (475
) from this pin to ground provides a
reference current used for the differential current-mode QX, nQX outputs.
27, 28 QC, nQC Output
Differential output pair C. HCSL interface levels.
30, 31 QD, nQD Output
Differential output pair D. HCSL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
3©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
Function Tables
Table 3A. nOEA Configuration Table
NOTE: nOEA is an asynchronous control.
Table 3C. nOEC Configuration Table
NOTE: nOEC is an asynchronous control.
Table 3B. nOEB Configuration Table
NOTE: nOEB is an asynchronous control.
Table 3D. nOED Configuration Table
NOTE: nOED is an asynchronous control.
Table 3E. SEL Configuration Table
NOTE: SEL is an asynchronous control
Input
OperationnOEA
0 Output QA, nQA is enabled.
1 (default) Output QA, nQA is in high-impedance state.
Input
OperationnOEC
0 Output QC, nQC is enabled.
1 (default) Output QC, nQC is in high-impedance state.
Input
OperationnOEB
0 Output QB, nQB is enabled.
1 (default) Output QB, nQB is in high-impedance state.
Input
OperationnOED
0 Output QD, nQD is enabled.
1 (default) Output QD, nQD is in high-impedance state.
Input
Selected InputSEL
0 (default) CLK0, nCLK0
1 CLK1, nCLK1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

831724AKILF

Mfr. #:
Buy 831724AKILF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:4 HCSL PCIe Clock Buffer
Lifecycle:
New from this manufacturer.
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