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831724AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
4©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Table 4B. LVCMOS/LVTTL Input DC Characteristics, V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Table 4C. Differential DC Characteristics, V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
37°C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.0 3.3 3.6 V
I
DD
Power Supply Current 128 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2.4 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current
nOEA, nOEB,
nOEC, nOED
V
IN =
V
DD
5µA
SEL V
IN =
V
DD
150 µA
I
IL
Input Low Current
nOEA, nOEB,
nOEC, nOED
V
IN
= 0V -150 µA
SEL V
IN
= 0V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input
High Current
CLK0, nCLK0, CLK1, nCLK1 V
IN =
V
DD
= 3.3V ± 0.3V 150 µA
I
IL
Input
Low Current
CLK0, CLK1 V
DD
= 3.3V ± 0.3V, V
IN
= 0V -5 µA
nCLK0, nCLK1 V
DD
= 3.3V ± 0.3V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 0.5 V
DD
– 0.85 V
5©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications, V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. The phase noise is dependent on the input signal source. The input signal was generated using a
Tektronix HFS9000 Stimulus System. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10
6
clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High
Band) and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
Symbol Parameter Test Conditions Minimum Typical Maximum
PCIe Industry
Specification Units
t
j
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
ƒ = 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
11.48 27 86 ps
t
REFCLK_HF_RMS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ = 100MHz,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
0.76 1.0 3.1 ps
t
REFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter RMS;
NOTE 2, 4
ƒ = 100MHz,
Low Band: 10kHz - 1.5MHz
0.15 1.3 3.0 ps
t
REFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
ƒ = 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.16 0.4 0.8 ps
6©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
Table 5B. HCSL AC Characteristics, V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between input paths on the same device, using the same input signal levels, measured at one specific output at the
differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: Measurement taken from differential waveform.
NOTE 6: Measurement from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 7: T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100 differential range. See Parameter Measurement Information Section.
NOTE 8: Measurement taken from single-ended waveform.
NOTE 9: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 10: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
Notes continued on next page.
NOTE 11: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
See Parameter Measurement Information Section
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 350 MHz
tjit
Buffer Additive Phase
Jitter, RMS
100MHz, Integration Range:
12kHz – 20MHz
0.357 0.480 ps
t
PD
Propagation Delay;
NOTE 1, 3
Any CLK, nCLK to any Q, nQ 2.7 3.9 ns
tsk(o) Output Skew; NOTE 3,15 Across all outputs 175 ps
tsk(i) Input Skew; NOTE 2, 3 165 ps
tsk(pp)
Part-to-Part Skew;
NOTE 3, 4
450 ps
MUX
ISOL
Mux Isolation ƒ = 100MHz 94 dB
Rising
Edge Rate
Rising Edge Rate;
NOTE 5, 6
f
OUT
125MHz 0.6 4.2 V/ns
f
OUT
125MHz 0.6 6.8 V/ns
Falling
Edge Rate
Falling Edge Rate;
NOTE 5, 6
f
OUT
125MHz 0.6 4.5 V/ns
f
OUT
125MHz 0.6 6.7 V/ns
T
STABLE
Time before VRB is
allowed; NOTE 5, 7
500 ps
V
RB
Ringback Voltage;
NOTE 5, 7
-100 100 mV
V
MAX
Absolute Maximum Output
Voltage; NOTE 8, 9
1150 mV
V
MIN
Absolute Minimum Output
Voltage; NOTE 8, 10
-300 mV
V
CROSS
Absolute Crossing Voltage;
NOTE 8, 11, 12
200 550 mV
V
CROSS
Total Variation of V
CROSS
over all edges;
NOTE 8, 11, 13
140 mV
odc
Output Duty Cycle;
NOTE 14
f
OUT
125MHz 46 54 %
f
OUT
125MHz 40 60 %
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

831724AKILF

Mfr. #:
Buy 831724AKILF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:4 HCSL PCIe Clock Buffer
Lifecycle:
New from this manufacturer.
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