7©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
NOTE 12: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 13: Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 14: Input duty cycle must be 50%.
NOTE 15: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
8©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower.
The phase noise is dependent on the input source and measurement
equipment. The source generator is the Rohde & Schwarz SMA
100A. Phase noise is measured using an Agilent E5052A Signal
Source Analyzer.
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.357ps (typical)
9©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
Parameter Measurement Information
3.3V HCSL Output Load AC Test Circuit 1
Differential Input Level
Output Skew
3.3V HCSL Output Load AC Test Circuit 2
Part-to-Part Skew
Propagation Delay
475Ω
33Ω
50Ω
50Ω
33Ω
49.9Ω
49.9Ω
HCSL
GND
2pF
2pF
Qx
nQx
0V
IREF
V
DD
3.3V±0.3V
V
DD
GND
nCLK[0, 1]
CLK[0, 1]
Qx
nQx
Qy
nQy
HCSL
GND
0V 0V
SCOP
E
IREF
V
DD
This load condition is used for I
DD,
tsk(o), tsk(pp), tsk(i), t
PD,
odc
and tjit measurements.
3.3V±0.3V
Qx
nQx
tsk(pp)
P
art 1
P
art 2
Qx
nQy
t
PD
nCLK[0, 1]
CLK[0, 1]
nQ[A:D]
Q[A:D]

831724AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:4 HCSL PCIe Clock Buffer
Lifecycle:
New from this manufacturer.
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