16©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER
PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
17©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
Recommended Termination
Figure 4A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output
types. All traces should be 50 impedance single-ended or 100
differential.
Figure 4A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 4B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0 to 33. All traces should be 50
impedance single-ended or 100 differential.
Figure 4B. Recommended Termination (where a point-to-point connection can be used)
0-0.2"
PCI Express
L1
L1
1-14"
Driver
Rs
0.5" Max
L3
L4
L2
L2
49.9 +/- 5%
22 to 33 +/-5%
Rt
L3
L4
L5
0.5 - 3.5"
L5
Connector
PCI Express
Add-in Card
PCI Express
0-0.2"
PCI Express
0-0.2"0-18"
L1
L1
Rs
Driver
0.5" Max
L3
L3
L2
L2
49.9 +/- 5%
0 to 33
0 to 33
Rt
18©2016 Integrated Device Technology, Inc Revision B November 16, 2016
831724 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 831724.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 831724 is the sum of the core power plus the power dissipated at the output(s).
The following is the power dissipation for V
DD
= 3.3V ± 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated at the output(s).
Total Power
MAX
= V
DD_MAX
* (I
DD_MAX
) = 3.6V * 128mA = 460.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37.0°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.4608W *37.0°C/W = 102.05°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
JA
for 32 Lead VFQFN, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W

831724AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:4 HCSL PCIe Clock Buffer
Lifecycle:
New from this manufacturer.
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