13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
OUTPUT ENABLE & DISABLE TIMING
VIH
OE
VIL
tOE & tOLZ
VCC
2
VCC
2
100mV
100mV
tOHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
VOH
V
CC
2
VCC
2
5994 drw04b
Output
Enable
Output
Disable
READ CHIP SELECT ENABLE & DISABLE TIMING
V
IH
RCS
V
IL
tENS
tENH
tRCSLZ
RCLK
VCC
2
VCC
2
100mV
100mV
tRCSHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
V
CC
2
VCC
2
5994 drw04c
NOTES:
1. REN is HIGH.
2. RCS is LOW.
NOTES:
1. REN is HIGH.
2. OE is LOW.
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T7285/72T7295/72T72105/72T72115 support two different
timing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is determined during
Master Reset, by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
the 8,193rd word for IDT72T7285, 16,385th word for IDT72T7295, 32,769th
word for IDT72T72105 and 65,537th word for IDT72T72115, respectively was
written into the FIFO. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed, the PAF will go LOW after (16,384-m) writes for the IDT72T7285,
(32,768-m) writes for the IDT72T7295, (65,536-m) writes for the IDT72T72105
and (131,072-m) writes for the IDT72T72115. The offset “m” is the full offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 16,384 writes for the IDT72T7285, 32,768 writes for the
IDT72T7295, 65,536 writes for the IDT72T72105 and 131,072 writes for the
IDT72T72115, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of
Table 2. This parameter is also user programmable. See section on Program-
mable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 8,194th
word for the IDT72T7285, 16,386th word for the IDT72T7295, 32,770th word
for the IDT72T72105 and 65,538th word for the IDT72T72115, respectively
was written into the FIFO. Continuing to write data into the FIFO will cause the
PAF to go LOW. Again, if no reads are performed, the PAF will go LOW
after (16,385-m) writes for the IDT72T7285, (32,769-m) writes for the
IDT72T7295, (65,537-m) writes for the IDT72T72105 and (131,073-m) writes
for the IDT72T72115, where m is the full offset value. The default setting for
these values are stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. D = 16,385 writes for the IDT72T7285, 32,769 writes for
the IDT72T7295, 65,537 writes for the IDT72T72105 and 131,073 writes for
the IDT72T72115, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 14, 15,
16 and 19.
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72T7285/
72T7295/72T72105/72T72115 have internal registers for these offsets. There
are eight default offset values selectable during Master Reset. These offset
values are shown in Table 2. Offset values can also be programmed into the
FIFO in one of two ways; serial or parallel loading method. The selection of the
loading method is done using the LD (Load) pin. During Master Reset, the state
of the LD input determines whether serial or parallel flag offset programming is
enabled. A HIGH on LD during Master Reset selects serial loading of offset
values. A LOW on LD during Master Reset selects parallel loading of offset
values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q
0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T7285/72T7295/72T72105/72T72115 can be configured during
the Master Reset cycle with either synchronous or asynchronous timing for PAF
and PAE flags by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see
Figure 25 for asynchronous PAF timing and Figure 26 for asynchronous PAE
timing.
IDT72T7285,72T7295,72T72105,72T72115
*LD FSEL1 FSEL0 Offsets n,m
H L L 1,023
LH L511
L L H 255
L L L 127
LHH63
HH L31
HL H15
HH H7
*LD FSEL1 FSEL0 Program Mode
H X X Serial
(3)
L X X Parallel
(4)
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.

72T72115L5BBI

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 2.5V 128K X 72 TERASYNC
Lifecycle:
New from this manufacturer.
Delivery:
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