7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
™™
™™
™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
PIN DESCRIPTION (CONTINUED)
Symbol Name I/O TYPE Description
PAE Programmable HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
Almost-Empty Flag OUTPUT Empty Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal
to offset n.
PAF Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
Almost-Full Flag OUTPUT the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal
to m.
PFM
(1)
Programmable LVTTL During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
Flag Mode INPUT PFM will select Synchronous Programmable flag timing mode.
PRS Partial Reset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
INPUT the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
Q0–Q71 Data Outputs HSTL-LVTTL Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, any unused output pins should not
OUTPUT be connected. Outputs are not 3.3V tolerant regardless of the state of OE and RCS.
RCLK/ Read Clock/ HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
RD Read Strobe INPUT reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has
been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be
tied LOW.
RCS Read Chip Select HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
INPUT a Master Reset or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
REN Read Enable HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enables RCLK for reading data from the
INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN
input should be tied LOW.
RHSTL
(1)
Read Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select INPUT required, this input must be tied HIGH. Otherwise it should be tied LOW.
RT Retransmit HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to
INPUT HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode or
programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to
the ‘mark’ location.
SCLK Serial Clock HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT SEN is enabled.
SEN Serial Enable HSTL-LVTTL SEN enables serial loading of programmable flag offsets.
INPUT
SHSTL System HSTL LVTTL All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select INPUT
TCK
(2)
JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
INPUT of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI
(2)
JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Input INPUT test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO
(2)
JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Output OUTPUT test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID
Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.
TMS
(2)
JTAG Mode HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
Select INPUT the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
