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72T72115L5BBI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
™™
™™
™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
IDT72T7285 IDT72T7295
0
1 to n
(1)
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,768
0
1 to n
(1)
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
IDT72T72105
0
1 to n
(1)
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
IDT72T7285 IDT72T7295
00 0
1 to n+1
1 to n+1
1 to n+1
(n+2) to 16,385
(n+2) to 32,769 (n+2) to 65,537
16,386 to (32,769-(m+1)) 32,770 to (65,537-(m+1))
65,538 to (131,073-(m+1))
(32,769-m) to 32,768
(65,537-m) to 65,536 (131,073-m) to 131,072
32,769 65,537 131,073
IDT72T72105 IDT72T72115
0
1 to n+1
(n+2) to 8,193
8,194 to (16,385-(m+1))
(16,385-m) to 16,384
16,385
IR PAF
HF
PAE OR
LH
HL H
LH
HL
L
LH
H
HL
LHLHL
L
L
LH L
HL
LH L
Number of
Words in
FIFO
TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE
FF PAF
HF
PAE EF
HH
HL L
HH
HL
H
HH
H
HH
HHL HH
H
L
LHH
LL
LHH
5994 drw05
IDT72T72115
0
1 to n
(1)
(n+1) to 65,536
65,537 to (131,072-(m+1))
(131,072-m) to 131,071
131,072
Number of
Words in
FIFO
NOTE:
1. See table 2 for values for n, m.
NOTE:
1. See table 2 for values for n, m.
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
™™
™™
™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Figure 3. Programmable Flag Offset Programming Sequence
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
WCLK RCLK
X
X
XX
X
X
XX
LD
0
0
X
1
1
1
0
WEN
0
1
1
0
X
1
1
REN
1
0
1
X
0
1
1X
SEN
1
1
1
X
X
X
0
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
Ending with Full Offset (MSB)
28 bits for the IDT72T7285
30 bits for the IDT72T7295
32 bits for the IDT72T72105
34 bits for the IDT72T72115
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
5994 drw06
SCLK
X
X
X
X
X
X
X
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
™™
™™
™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (PAE)
# of Bits Used
234
5
67
910111213
14
1516
1st Parallel Offset Write/Read Cycle
234
56781213
1415
16
11
Interspersed
Parity
10
1
1
8
D/Q35 D/Q19
9
D/Q17
D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
# of Bits Used
234
5
67
910111213
14
15
16
2nd Parallel Offset Write/Read Cycle
234
56781213
1415
16
11
Interspersed
Parity
10
1
1
8
9
x36 Bus Width
Non-Interspersed
Parity
Non-Interspersed
Parity
D/Q35 D/Q19
# of Bits Used:
14 bits for the IDT72T7285
15 bits for the IDT72T7295
16 bits for the IDT72T72105
17 bits for the IDT72T72115
Note: All unused input bits
are don’t care.
5994 drw07
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (PAE)
# of Bits Used
234
5
67
910111213
14
15
16
1st Parallel Offset Write/Read Cycle
234
56781213
1415
16
11
Interspersed
Parity
10
1
1
8
D/Q71 D/Q19
9
D/Q17
D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
# of Bits Used
234
5
67
910111213
14
15
16
2nd Parallel Offset Write/Read Cycle
234
56781213
1415
16
11
Interspersed
Parity
10
1
1
8
9
x72 Bus Width
Non-Interspersed
Parity
Non-Interspersed
Parity
D/Q71 D/Q19
17
17
17
17
17
17
17
17
D/Q17
D/Q0D/Q16
EMPTY OFFSET (LSB) REGISTER (PAE)
Data Inputs/Outputs
# of Bits Used
1234
56789101112131415
EMPTY OFFSET (MSB) REGISTER (PAE)
Data Inputs/Outputs
17
16
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
Data Inputs/Outputs
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
1234
5678
10
11
1213
1415
9
FULL OFFSET (LSB) REGISTER (PAF)
12345678910
1112
13
141516
1
2345678
1011121314
15
9
FULL OFFSET (MSB) REGISTER (PAF)
17
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
D/Q0
D/Q0
D/Q8
D/Q8
16
16
17
17
D/Q17
D/Q16
D/Q17
D/Q16
D/Q17
D/Q16
x18 Bus Width
NOTE:
1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

72T72115L5BBI

Mfr. #:
Buy 72T72115L5BBI
Manufacturer:
IDT
Description:
FIFO 2.5V 128K X 72 TERASYNC
Lifecycle:
New from this manufacturer.
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