LTC2228/LTC2227/LTC2226
16
222876fb
APPLICATIONS INFORMATION
CONVERTER OPERATION
As shown in Figure 1, the LTC2228/LTC2227/LTC2226
is a CMOS pipelined multi-step converter. The converter
has six pipelined ADC stages; a sampled analog input will
result in a digitized value fi ve cycles later (see the Timing
Diagram section). For optimal AC performance the analog
inputs should be driven differentially. For cost sensitive
applications, the analog inputs can be driven single-ended
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2228/LTC2227/LTC2226 has two
phases of operation, determined by the state of the CLK
input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifi er.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplifi ed and
output by the residue amplifi er. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifi er which drives the fi rst pipelined ADC
stage. The fi rst stage acquires the output of the S/H dur-
ing this high phase of CLK. When CLK goes back low, the
fi rst stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
third stage. An identical process is repeated for the third,
fourth and fi fth stages, resulting in a fi fth stage residue
that is sent to the sixth stage ADC for fi nal evaluation.
Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2228/
LTC2227/LTC2226 CMOS differential sample-and-hold.
The analog inputs are connected to the sampling capaci-
tors (C
SAMPLE
) through NMOS transistors. The capacitors
shown attached to each input (C
PARASITIC
) are the summa-
tion of all other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage. When
CLK transitions from low to high, the sampled input voltage
is held on the sampling capacitors. During the hold phase
when CLK is high, the sampling capacitors are disconnected
from the input and the held voltage is passed to the ADC
core for processing. As CLK transitions from high to low,
the inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small, the charging glitch seen at the input will
be small. If the input change is large, such as the change
seen with input frequencies near Nyquist, then a larger
charging glitch will be seen.
V
DD
V
DD
V
DD
15Ω
15Ω
C
PARASITIC
1pF
C
PARASITIC
1pF
C
SAMPLE
4pF
C
SAMPLE
4pF
LTC2228/27/26
A
IN
+
A
IN
–
CLK
222876 F02
Figure 2. Equivalent Input Circuit
