LTC2228/LTC2227/LTC2226
22
222876fb
APPLICATIONS INFORMATION
digital outputs of the LTC2228/LTC2227/LTC2226 should
drive a minimal capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2228/LTC2227/LTC2226
parallel digital output can be selected for offset binary
or 2’s complement format. Connecting MODE to GND or
1/3V
DD
selects offset binary output format. Connecting
MODE to 2/3V
DD
or V
DD
selects 2’s complement output
format. An external resistor divider can be used to set the
1/3V
DD
or 2/3V
DD
logic values. Table 2 shows the logic
states for the MODE pin.
Table 2. MODE Pin Function
MODE PIN OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0 Offset Binary Off
1/3V
DD
Offset Binary On
2/3V
DD
2’s Complement On
V
DD
2’s Complement Off
Overfl ow Bit
When OF outputs a logic high the converter is either over-
ranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply, then OV
DD
should be tied to that same
1.8V supply.
OV
DD
can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OV
DD
. The logic outputs
will swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors
have to recharge and stabilize. Connecting SHDN to V
DD
and OE to GND results in nap mode, which typically dis-
sipates 15mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Grounding and Bypassing
The LTC2228/LTC2227/LTC2226 require a printed circuit
board with a clean, unbroken ground plane. A multilayer
board with an internal ground plane is recommended.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much
as possible. In particular, care should be taken not to
run any digital track alongside an analog signal track or
underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V
DD
, OV
DD
, V
CM
, REFH, and REFL pins. Bypass capaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1μF capacitor between REFH
and REFL. This capacitor should be placed as close to the
device as possible (1.5mm or less). A size 0402 ceramic
capacitor is recommended. The large 2.2μF capacitor be-
tween REFH and REFL can be somewhat further away. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
