LTC2228/LTC2227/LTC2226
20
222876fb
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 3.8dB. See the Typical Performance
Characteristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or
TTL level signal. A sinusoidal clock can also be used
along with a low jitter squaring circuit before the CLK pin
(Figure 11).
The noise performance of the LTC2228/LTC2227/LTC2226
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digi-
tizing high input frequencies, use as large an amplitude
as possible. Also, if the ADC is clocked with a sinusoidal
signal, fi lter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bear-
ing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass fi lter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for refl ections.
APPLICATIONS INFORMATION
CLK
1k
1k
FERRITE
BEAD
CLEAN
SUPPLY
222876 F11
LTC2228/
LTC2227/
LTC2226
0.1μF
0.1μF
SINUSOIDAL
CLOCK INPUT
4.7μF
NC7SVU04
50Ω
Figure 11. Single-Ended CLK Drive
CLK
100Ω
0.1μF
4.7μF
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
223876 F12
LTC2238/
LTC2237/
LTC2236
CLK
5pF-30pF
ETC1-1T
0.1μF
V
CM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
223876 F13
LTC2238/
LTC2237/
LTC2236
Figure 13. LVDS or PECL CLK Drive Using a Transformer
Figure 12. CLK Drive Using an LVDS or PECL-to-CMOS Converter
