ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 21 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.3.3 Common-mode output voltage (V
O(cm)
)
A 0.1 F filter capacitor should be connected between pin VCM and ground to ensure a
low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to
set the common-mode reference for the analog inputs, for instance via a transformer
middle point.
11.3.4 Biasing
The common-mode input voltage (V
I(cm)
) on pins INP and INM should be set externally to
0.5V
DDA
for optimal performance and should always be between 0.9 V and 2 V.
11.4 Clock input
11.4.1 Drive modes
The ADC1210S can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
Fig 25. Equivalent schematic of the common-mode reference circuit
1.5 V
VCM
0.1 μF
package ESD parasitics
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COMMON-MODE
REFERENCE
ADC core
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 26. LVCMOS single-ended clock input
LVCMOS
clock input
CLKP
CLKM
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LVCMOS
clock input
CLKP
CLKM
