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ADC1210S105HN/C1:5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 25 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.5.3 DAta Valid (DAV) output clock
A data valid output clock signal (DAV) can be used to capture the data delivered by the
ADC1210S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in
Figure 4
and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR
(bit FASTOTR = logic 1; see Table 29
). In this mode, the latency of OTR is reduced to only
four clock cycles. The Fast OTR detection threshold (below full-scale) can be
programmed via bits FASTOTR_DET[2:0].
11.5.5 Digital offset
By default, the ADC1210S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see Table 25
).
11.5.6 Test patterns
For test purposes, the ADC1210S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26
). A custom test pattern
can be defined by the user (TESTPAT_USER[11:0]; see Table 27
and Table 28) and is
selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted
regardless of the analog input.
Table 14. LVDS DDR output register 2
LVDS_INT_TER[2:0] Resistor value ()
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 60
Table 15. Fast OTR register
FASTOTR_DET[2:0] Detection level (dB)
000 20.56
001 16.12
010 11.02
011 7.82
100 5.49
101 3.66
110 2.14
111 0.86
ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 26 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.5.7 Output codes versus input voltage
11.6 Serial peripheral interface
11.6.1 Register description
The ADC1210S serial interface is a synchronous serial communications port that allows
easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
Pin SCLK is the serial clock input and CS
is the chip select pin.
Each read/write operation is initiated by a LOW level on pin CS
. A minimum of three bytes
is transmitted (two instruction bytes and at least one data byte). The number of data bytes
is determined by the value of bits W1 and W2 (see Table 18
).
[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18
).
Table 16. Output codes
V
INP
V
INM
Offset binary Two’s complement OTR pin
< 1 0000 0000 0000 1000 0000 0000 1
1.0000000 0000 0000 0000 1000 0000 0000 0
0.9995117 0000 0000 0001 1000 0000 0001 0
0.9990234 0000 0000 0010 1000 0000 0010 0
0.9985352 0000 0000 0011 1000 0000 0011 0
0.9980469 0000 0000 0100 1000 0000 0100 0
.... .... .... 0
0.0009766 0111 1111 1110 1111 1111 1110 0
0.0004883 0111 1111 1111 1111 1111 1111 0
0.0000000 1000 0000 0000 0000 0000 0000 0
+0.0004883 1000 0000 0001 0000 0000 0001 0
+0.0009766 1000 0000 0010 0000 0000 0010 0
.... .... .... 0
+0.9980469 1111 1111 1011 0111 1111 1011 0
+0.9985352 1111 1111 1100 0111 1111 1100 0
+0.9990234 1111 1111 1101 0111 1111 1101 0
+0.9995117 1111 1111 1110 0111 1111 1110 0
+1.0000000 1111 1111 1111 0111 1111 1111 0
> +1 1111 1111 1111 0111 1111 1111 1
Table 17. Instruction bytes for the SPI
MSB LSB
Bit 76543210
Description R/W
[1]
W1
[2]
W0
[2]
A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 27 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS
in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS
indicates the end of data transmission.
11.6.2 Default modes at start-up
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS
triggers a transition to SPI control mode. When the ADC1210S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 33
). Once in SPI control mode, the output data standard
can be changed via bit LVDS_CMOS
in Table 23.
When the ADC1210S enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT[1:0] in Table 23
.
Table 18. Number of data bytes to be transferred after the instruction bytes
W1 W0 Number of bytes transmitted
001 byte
012 bytes
103 bytes
1 1 4 bytes or more
Fig 32. SPI mode timing
SCLK
SDIO
R/W
W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0D0 D7 D6 D5 D4
Instruction bytes Register N (data) Register N + 1 (data)
005aaa062
CS
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ADC1210S105HN/C1:5

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