ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 34 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Table 31. LVDS DDR output register 1 (address 0021h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - 00 not used
5 DAVI_x2_EN R/W double LVDS current for DAV LVDS buffer
0 disabled
1 enabled
4 to 3 DAVI[1:0] R/W LVDS current for DAV LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
2 DATAI_x2_EN R/W double LVDS current for DATA LVDS buffer
0 disabled
1 enabled
1 to 0 DATAI[1:0] R/W LVDS current for DATA LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
Table 32. LVDS DDR output register 2 (address 0022h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 BIT_BYTE_WISE R/W DDR mode for LVDS output
0 bit wise (even data bits output on DAV rising edge/odd
data bits output on DAV falling edge)
1 byte wise (MSB data bits output on DAV rising edge/LSB data
bits output on DAV falling edge)
2 to 0 LVDS_INT_TER[2:0] R/W internal termination for LVDS buffer (DAV and DATA)
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 60
