ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 23 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table 21
). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see Table 21
), the circuit can handle signals with duty
cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.4.4 Clock input divider
The ADC1210S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = logic 1; see Table 21
). This feature allows the user to deliver a
higher clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to
logic 0 (see Table 23
).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 29
. The buffer is powered by a separate power
supply, pins OGND and VDDO, to ensure 1.8 V to 3.3 V compatibility and is isolated from
the ADC core. Each buffer can be loaded by a maximum of 10 pF.
Fig 29. CMOS digital output buffer
VDDO
ESD PackageParasitics
OGND
Dx
005aaa057
50 Ω
LOGIC
DRIVER
