1. General description
The ADC1210S is a single-channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1210S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode
because of a separate digital output supply. It supports the Low Voltage Differential
Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated
Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device
also includes a programmable full-scale SPI to allow a flexible input voltage range from
1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to
input frequencies of 170 MHz or more, the ADC1210S is ideal for use in communications,
imaging and medical applications.
2. Features and benefits
3. Applications
ADC1210S series
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
CMOS or LVDS DDR digital outputs
Rev. 2 — 23 December 2010 Product data sheet
SNR, 70 dBFS; SFDR, 86 dBc Input bandwidth, 600 MHz
Sample rate up to 125 Msps Power dissipation, 430 mW at 80 Msps
12-bit pipelined ADC core Serial Peripheral Interface (SPI)
Clock input divided by 2 for less jitter Duty cycle stabilizer
Single 3 V supply Fast OuT-of-Range (OTR) detection
Flexible input voltage range: 1 V (p-p) to
2 V (p-p)
Offset binary, two’s complement, gray
code
CMOS or LVDS DDR digital outputs Power-down and Sleep modes
Pin compatible with the ADC1410S
series and the ADC1010S series
HVQFN40 package
Wireless and wired broadband
communications
Portable instrumentation
Spectral analysis Imaging systems
Ultrasound equipment Software defined radio
ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 2 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number f
s
(Msps) Package
Name Description Version
ADC1210S125HN/C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1210S105HN/C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1210S080HN/C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
ADC1210S065HN/C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 6 0.85 mm
SOT618-1
Fig 1. Block diagram
ADC1210S
SPI INTERFACE
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
12-BIT
PIPELINED
T/H
INPUT
STAGE
INP
OTR
CS
SDIO/ODS
SCLK/DFS
PWD
REFT
CMOS:
D11 to D0
or
LVDS DDR:
D10_D11_M to D0_D1_M
D10_D11_P to D0_D1_P
INM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
REFB
CLKMCLKP
SENSE
VREF
VCM
005aaa131
OE
CMOS:
DAV
or
LVDS DDR:
DAVP
DAVM
ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 3 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration with CMOS digital outputs
selected
Fig 3. Pin configuration with LVDS DDR digital
outputs selected
ADC1210S
HVQFN40
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
n.c.
VDDA
INP
INM
AGND
VDDA
VCM
AGND
REFT
REFB
VDDA
CLKP
CLKM
DEC
PWD
D11
D10
D9
D8
VREF
SENSE
SDIO/ODS
SCLK/DFS
OTR
OGND
VDDO
n.c.
DAV
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
AGND
terminal 1
index area
Transparent top view
005aaa132
OE
CS
ADC1210S
HVQFN40
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
n.c.
n.c.
VDDA
INP
INM
AGND
VDDA
VCM
AGND
REFT
REFB
VDDA
CLKP
CLKM
DEC
PWD
D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
VREF
SENSE
SDIO/ODS
SCLK/DFS
OTR
OGND
VDDO
DAVP
DAVM
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
AGND
terminal 1
index area
Transparent top view
005aaa133
OE
CS
Table 2. Pin description (CMOS digital outputs)
Symbol Pin Type
[1]
Description
REFB 1 O bottom reference
REFT 2 O top reference
AGND 3 G analog ground
VCM 4 O common-mode output voltage
VDDA 5 P analog power supply
AGND 6 G analog ground
INM 7 I complementary analog input
INP 8 I analog input
AGND 9 G analog ground
VDDA 10 P analog power supply
VDDA 11 P analog power supply
CLKP 12 I clock input
CLKM 13 I complementary clock input
DEC 14 O regulator decoupling node
OE
15 I output enable, active LOW
PWD 16 I power-down, active HIGH

ADC1210S125HN/C1:5

Mfr. #:
Manufacturer:
Description:
IC ADC 12BIT PIPELINED 40HVQFN
Lifecycle:
New from this manufacturer.
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