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ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 10 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
[1] Typical values measured at V
DDA
=3V, V
DDO
=1.8V, T
amb
=25C and C
L
= 5 pF; minimum and maximum values are across the full temperature range T
amb
= 40 C to +85 C
at V
DDA
=3V, V
DDO
= 1.8 V; V
INP
V
INM
= 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
[2] Measured between 20 % to 80 % of V
DDO
.
[3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV.
LVDS DDR mode timing output: pins D10_D11_P to D0_D1_P, D10_D11_M to D0_D1_M, DAVP and DAVM
t
PD
propagation
delay
DATA 3.3 5.1 7.6 2.9 4.6 7.1 2.5 4.2 6.8 2.2 4.0 6.6 ns
DAV - 2.8 - - 2.5 - - 2.3 - - 2.2 - ns
t
su
set-up time - 5.4 - - 4.1 - - 2.6 - - 1.9 - ns
t
h
hold time - 2.2 - - 2.0 - - 1.8 - - 1.7 - ns
t
r
rise time DATA
[3]
0.5 - 5 0.5 - 5 0.5 - 5 0.5 - 5 ns
DAV 0.18 - 2.40.18 - 2.40.18 - 2.40.18 - 2.4ns
t
f
fall time DATA
[3]
0.15 - 1.6 0.15 - 1.6 0.15 - 1.6 0.15 - 1.6 ns
Table 8. Clock input and digital output timing characteristics
[1]
…continued
Symbol Parameter Conditions ADC1210S065 ADC1210S080 ADC1210S105 ADC1210S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
