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ADC1210S125HN/C1:5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 7 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
[1] Typical values measured at V
DDA
=3V, V
DDO
=1.8V, T
amb
=25C and C
L
= 5 pF; minimum and maximum values are across the full
temperature range T
amb
= 40 C to +85 C at V
DDA
=3V, V
DDO
= 1.8 V; V
INP
V
INM
= 1 dBFS; internal reference mode; applied to
CMOS and LVDS interface; unless otherwise specified.
Digital outputs, CMOS mode: pins D11 to D0, OTR, DAV
Output levels, V
DDO
= 3 V
V
OL
LOW-level output voltage OGND - 0.2V
DDO
V
V
OH
HIGH-level output voltage 0.8V
DDO
-V
DDO
V
C
O
output capacitance high impedance; OE =HIGH - 3 - pF
Output levels, V
DDO
= 1.8 V
V
OL
LOW-level output voltage OGND - 0.2V
DDO
V
V
OH
HIGH-level output voltage 0.8V
DDO
-V
DDO
V
Digital outputs, LVDS mode: pins D11P to D0P, D11M to D0M, DAVP and DAVM
Output levels, V
DDO
= 3 V only, R
L
=100
V
O(offset)
output offset voltage output buffer current set to
3.5 mA
-1.2-V
V
O(dif)
differential output voltage output buffer current set to
3.5 mA
-350-mV
C
O
output capacitance - 3 - pF
Analog inputs: pins INP and INM
I
I
input current 5- +5A
R
i(dif)
differential input resistance - 19.8 - k
C
i(dif)
differential input capacitance - 2.8 - pF
V
I(cm)
common-mode input voltage V
INP
=V
INM
1.1 1.5 2.5 V
B
i
input bandwidth - 650 - MHz
V
I(dif)
differential input voltage peak-to-peak 1 - 2 V
Common mode output voltage: pin VCM
V
O(cm)
common-mode output voltage - V
DDA
/2 - V
I
O(cm)
common-mode output current - 4 - mA
I/O reference voltage: pin VREF
V
VREF
voltage on pin VREF output 0.5 - 1 V
input 0.5 - 1 V
Accuracy
INL integral non-linearity - 0.25 - LSB
DNL differential non-linearity guaranteed no missing codes 0.25 0.12 +0.25 LSB
E
offset
offset error - 2- mV
E
G
gain error full-scale 0.5 %
Supply
PSRR power supply rejection ratio 200 mV (p-p) on V
DDA
; f
i
=DC - 54 - dB
Table 6. Static characteristics
[1]
…continued
Symbol Parameter Conditions Min Typ Max Unit
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 8 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7. Dynamic characteristics
[1]
Symbol Parameter Conditions ADC1210S065 ADC1210S080 ADC1210S105 ADC1210S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Analog signal processing
2H
second harmonic
level
f
i
= 3 MHz - 87 - - 87 - - 86 - - 88 - dBc
f
i
=30MHz - 86 - - 86 - - 86 - - 87 - dBc
f
i
=70MHz - 85 - - 85 - - 84 - - 85 - dBc
f
i
= 170 MHz - 82 - - 82 - - 81 - - 83 - dBc
3H
third harmonic
level
f
i
= 3 MHz - 86 - - 86 - - 85 - - 87 - dBc
f
i
=30MHz - 85 - - 85 - - 85 - - 86 - dBc
f
i
=70MHz - 84 - - 84 - - 83 - - 84 - dBc
f
i
= 170 MHz - 81 - - 81 - - 80 - - 82 - dBc
THD total harmonic
distortion
f
i
= 3 MHz - 83 - - 83 - - 82 - - 84 - dBc
f
i
=30MHz - 82 - - 82 - - 82 - - 83 - dBc
f
i
=70MHz - 81 - - 81 - - 80 - - 81 - dBc
f
i
= 170 MHz - 78 - - 78 - - 77 - - 79 - dBc
ENOB effective number
of bits
f
i
= 3 MHz - 11.3 - - 11.3 - - 11.3 - - 11.3 - bits
f
i
= 30 MHz - 11.3 - - 11.3 - - 11.3 - - 11.2 - bits
f
i
= 70 MHz - 11.2 - - 11.2 - - 11.2 - - 11.2 - bits
f
i
= 170 MHz - 11.1 - - 11.1 - - 11.1 - - 11.1 - bits
SNR signal-to-noise
ratio
f
i
= 3 MHz - 70.0 - - 69.9 - - 69.8 - - 69.6 - dBFS
f
i
= 30 MHz - 69.5 - - 69.5 - - 69.5 - - 69.4 - dBFS
f
i
= 70 MHz - 69.2 - - 69.2 - - 69.1 - - 69.0 - dBFS
f
i
= 170 MHz - 68.8 - - 68.8 - - 68.7 - - 68.6 - dBFS
SFDR spurious-free
dynamic range
f
i
= 3 MHz - 86 - - 86 - - 85 - - 87 - dBc
f
i
=30MHz - 85 - - 85 - - 85 - - 86 - dBc
f
i
=70MHz - 84 - - 84 - - 83 - - 84 - dBc
f
i
= 170 MHz - 81 - - 81 - - 80 - - 82 - dBc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
ADC1210S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 23 December 2010 9 of 39
NXP Semiconductors
ADC1210S series
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
[1] Typical values measured at V
DDA
=3V, V
DDO
=1.8V, T
amb
=25C and C
L
= 5 pF; minimum and maximum values are across the full temperature range T
amb
= 40 C to +85 C
at V
DDA
=3V, V
DDO
= 1.8 V; V
INP
V
INM
= 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
10.2 Clock and digital output timing
IMD Intermodulation
distortion
f
i
= 3 MHz - 89 - - 89 - - 88 - - 89 - dBc
f
i
=30MHz - 88 - - 88 - - 88 - - 88 - dBc
f
i
=70MHz - 87 - - 87 - - 86 - - 86 - dBc
f
i
= 170 MHz - 84 - - 85 - - 83 - - 84 - dBc
Table 7. Dynamic characteristics
[1]
…continued
Symbol Parameter Conditions ADC1210S065 ADC1210S080 ADC1210S105 ADC1210S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 8. Clock input and digital output timing characteristics
[1]
Symbol Parameter Conditions ADC1210S065 ADC1210S080 ADC1210S105 ADC1210S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
f
clk
clock
frequency
40 - 65 60 - 80 75 - 105 100 - 125 MHz
t
lat(data)
data latency
time
-13.5- -13.5- -13.5- -13.5-clock
cycles
clk
clock duty
cycle
DCS_EN=logic1 305070305070305070305070%
DCS_EN=logic0 455055455055455055455055%
t
d(s)
sampling
delay time
- 0.8 - - 0.8 - - 0.8 - - 0.8 - ns
t
wake
wake-up time -76- -76- -76- -76-s
CMOS mode timing output: pins D11 to D0 and DAV
t
PD
propagation
delay
DATA 13.6 14.9 16.4 11.9 12.9 14.4 8.0 10.8 12.4 8.2 9.7 11.3 ns
DAV - 4.2 - - 3.6 - - 3.3 - - 3.4 - ns
t
su
set-up time - 12.5 - - 9.8 - - 6.8 - - 5.6 - ns
t
h
hold time - 3.4 - - 3.3 - - 3.1 - - 2.8 - ns
t
r
rise time DATA
[2]
0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 ns
DAV 0.26 - 2.40.26 - 2.40.26 - 2.40.26 - 2.4ns
t
f
fall time DATA
[2]
0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

ADC1210S125HN/C1:5

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IC ADC 12BIT PIPELINED 40HVQFN
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