ADC1210S125HN/C1:5 Datasheet ADC1210S065HN/C1,5, ADC1210S080HN/C1:5, ADC1210S105HN/C1:5 | P28-P30

Product data sheet Rev. 2 — 23 December 2010 28 of 39

NXP Semiconductors

ADC1210S series

Single 12-bit ADC; CMOS or LVDS DDR digital outputs

Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR

Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS

SDIO

(CMOS LVDS DDR)

SCLK

(Data format)

Offset binary, LVDS DDR

default mode at start-up

005aaa063

SDIO

(CMOS LVDS DDR)

SCLK

(Data format)

two's complement, CMOS

default mode at start-up

005aaa064

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Product data sheet Rev. 2 — 23 December 2010 29 of 39

NXP Semiconductors

ADC1210S series

Single 12-bit ADC; CMOS or LVDS DDR digital outputs

11.6.3 Register allocation map

Table 19. Register allocation map

Addr

Hex

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin

0005 Reset and

operating mode

R/W SW_RST RESERVED[2:0] - - OP_MODE[1:0] 0000

0000

0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV DCS_EN 0000

0001

0008 Internal reference R/W - - - - INTREF_EN INTREF[2:0] 0000

0000

0011 Output data

standard

R/W - - - LVDS_

CMOS

OUTBUF OUTBUS_SWAP DATA_FORMAT[1:0] 0000

0000

0012 Output clock R/W - - - - DAVINV DAVPHASE[2:0] 0000

1110

0013 Offset R/W - - DIG_OFFSET[5:0] 0000

0000

0014 Test pattern 1 R/W - - - - - TESTPAT_SEL[2:0] 0000

0000

0015 Test pattern 2 R/W TESTPAT_USER[11:4] 0000

0000

0016 Test pattern 3 R/W TESTPAT_USER[3:0] - - - - 0000

0000

0017 Fast OTR R/W - - - - FASTOTR FASTOTR_DET[2:0] 0000

0000

0020 CMOS output R/W - - - - DAV_DRV[1:0] DATA_DRV[1:0] 0000

1110

0021 LVDS DDR O/P 1 R/W - - DAVI_x2_EN DAVI[1:0] DATAI_x2_EN DATAI[1:0] 0000

0000

0022 LVDS DDR O/P 2 R/W - - - - BI_BYTE_WISE LVDS_INT_TER[2:0] 0000

0000

Product data sheet Rev. 2 — 23 December 2010 30 of 39

NXP Semiconductors

ADC1210S series

Single 12-bit ADC; CMOS or LVDS DDR digital outputs

Table 20. Reset and operating mode control register (address 0005h) bit description

Default values are highlighted.

Bit Symbol Access Value Description

7 SW_RST R/W reset digital section

0no reset

1 performs a reset of the SPI registers

6 to 4 RESERVED[2:0] 000 reserved

3 to 2 - 00 not used

1 to 0 OP_MODE[1:0] R/W operating mode

00 normal (power-up)

01 power-down

10 sleep

11 normal (power-up)

Table 21. Clock control register (address 0006h) bit description

Default values are highlighted.

Bit Symbol Access Value Description

7 to 5 - 000 not used

4 SE_SEL R/W single-ended clock input pin select

0CLKM

1CLKP

3 DIFF_SE R/W differential/single-ended clock input select

0 fully differential

1 single-ended

2 - 0 not used

1 CLKDIV R/W clock input divide by 2

0disabled

1 enabled

0 DCS_EN R/W duty cycle stabilizer

0 disabled

1 enabled

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ADC1210S125HN/C1:5

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ADC1210S125HN/C1:5

ADC1210S125HN/C1:5

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