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82V3911AUG8

P1-P3P4-P6P7-P9P10-P12
1 July 1, 2013
IDT82V3911
Short Form
Datasheet
2013 Integrated Device Technology, Inc. DSC-7238/-
Synchronous Ethernet Two-Channel
PLL for 10GbE and 40GbE
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
FEATURES
HIGHLIGHTS
• Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter
requirements of leading PHYs supporting 10GBASE-R, 10GBASE-
W, 40GBASE-R, OC-192 and STM-64
• Supports ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)
compliant equipment
• Supports clock generation for IEEE-1588 applications
• Generates SyncE interface clocks (1GE, 10GE, and 40GE)
MAIN FEATURES
• Provides an integrated solution for reference switching, frequency
translation and jitter attenuation for SyncE and SONET/SDH inter-
faces
• Integrates 2 DPLLs, one for the transmit path and one for the
receive path
• Selectable DPLL bandwidth: 18 Hz and 35 Hz
• Integrates 2 jitter attenuating APLLs to generate ultra-low jitter
clocks
• Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN-
PHY
• Supports up to two crystal connections, allowing each APLL to
support up to two modes of operation
• Supports input and output clocks covering a wide range of frequen-
cies
• Provides IN3, IN4, IN7,IN6 input CMOS clocks whose frequen-
cies range from 2 kHz to 156.25 MHz
• Provides IN1 and IN2 input differential clocks whose frequencies
range from 2 kHz to 625 MHz
• Provides OUT1 to OUT5 output CMOS clocks whose frequency
range from 1PPS to 125 MHz
• Provides OUT6~OUT9 output differential clocks whose fre-
quency range from 25 MHz to 644.53125 MHz
• Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal,
and a 1PPS, 2 kHz or 8 kHz frame sync output signal
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine. Automatic mode switch supports Free-
Run, Locked and Holdover modes
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail-
ure
• Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
• Supports LVPECL/LVDS and CMOS input/output technologies
• Supports master clock calibration
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom-
mendations
OTHER FEATURES
• I2C Microprocessor interface
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 1mm ball pitch CABGA green package
APPLICATIONS
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• Central Office Timing Source and Distribution
• DWDM cross-connect and transmission equipment
• IP core routers and access equipment
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipment
IDT82V3911 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
Description 2 July 1, 2013
DESCRIPTION
The 82V3911 Synchronous Ethernet (SyncE) Two-channel PLL is a
jitter attenuating device with rate conversion and reference switching
capabilities; its ultra-low jitter output clocks are used to directly synchro-
nize 10GBASE-R/10GBASE-W and OC-192/STM-64 PHYs and
40GBASE-R PHYs in Synchronous Ethernet and SONET/SDH equip-
ment. When the 82V3911 is locked to a Synchronous Equipment Timing
Source (SETS) that meets the requirements of ITU-T G.8262, G.813 or
Telcordia GR-253-CORE Stratum 3 or SONET Minimum Clock the
clocks generated by the 82V3911 will also meet those requirements.
The two 82V3911 timing channels are defined by independent Digital
PLLs (DPLLs) with embedded clock synthesizers. The two independent
timing channels allow the 82V3911 to synchronize transmit interfaces
with the selected system backplane clock, and to simultaneously provide
a recovered clock from a selected receive interface to the system back-
plane. DPLL1 is preferred for synchronizing transmit interfaces because
it has the more sophisticated holdover mode.
Both DPLLs support three primary operating modes: Free-Run,
Locked and Holdover. In Free-Run mode the DPLLs generate clocks
based on the master clock alone. In Locked mode the DPLLs filter refer-
ence clock jitter with one of the following selectable bandwidths: 18 Hz
or 35 Hz. In Locked mode the long-term DPLL frequency accuracy is the
same as the long term frequency accuracy of the selected input refer-
ence. In Holdover mode the DPLL uses frequency data acquired while in
Locked mode to generate accurate frequencies when input references
are not available.
The 82V3911 requires a 12.8 MHz master clock for its reference
monitors and other digital circuitry. The frequency accuracy of the mas-
ter clock determines the frequency accuracy of the DPLLs in Free-Run
mode. The frequency stability of the master clock determines the fre-
quency stability of the DPLLs in Free-Run mode and in Holdover mode.
The 82V3911 provides four single ended reference inputs and two
differential reference inputs that can operate at common Ethernet,
SONET/SDH and PDH frequencies and other frequencies. The refer-
ences are continually monitored for loss of signal and for frequency off-
set per user programmed thresholds. All of the references are available
to both DPLLs. The active reference for each DPLL is determined by
forced selection or by automatic selection based on user programmed
priorities and locking allowances and based on the reference monitors.
The 82V3911 can accept a clock reference and a phase locked
external sync signal as a pair. DPLL1 can lock to the reference clock
input and align its frame sync and multi-frame sync outputs with the
paired external sync input. The device provides to two external sync
inputs that can be associated with any of the six reference inputs to cre-
ate up to two pairs. The external sync signals can have a frequency of 1
Hz, 2 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame
sync and multi-frame sync outputs with an external sync input without
the need use a low bandwidth setting to lock directly to an external sync
input.
The clocks synthesized by the 82V3911 DPLLs can be passed
through either of the two independent voltage controlled crystal oscillator
(VCXO) based jitter attenuating analog PLLs (APLLs). Both APLLs drive
two independent dividers that have differential outputs. The APLLs use
external crystal resonators with resonant frequencies equal to the APLL
base frequency divided by 25. Both APLLs can be provisioned with one
or two selectable crystal resonators to support up to two base frequen-
cies per APLL. The output clocks generated by the APLLs exhibit jitter
below 0.30ps RMS over the integration range 10 kHz to 20 MHz for most
output frequencies.
IDT82V3911 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
Functional Block Diagram 3 July 1, 2013
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
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P1-P3P4-P6P7-P9P10-P12

82V3911AUG8

Mfr. #:
Buy 82V3911AUG8
Manufacturer:
IDT
Description:
Clock Generators & Support Products SyncE Two Chan PLL for 10GbE and 40GbE
Lifecycle:
New from this manufacturer.
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