IDT82V3911 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
Pin Description 7 July 1, 2013
XTAL1_IN A3 I Analog
Crystal oscillator 1 input.
Determines first of two frequency families (Sonet/SDH, Ethernet or Ethernet*66/64)
available for APLL1. Connect to ground if XTAL1 is not used.
XTAL1_OUT B3 O Analog
Crystal oscillator 1 output.
Leave open if XTAL1 is not used.
XTAL2_IN P10 I Analog
Crystal oscillator 2 input.
Determines first of two frequency families (chosen from Sonet/SDH, Ethernet or Ether-
net*66/64) available for APLL2. Connect to ground if XTAL2 is not used
XTAL2_OUT N10 O Analog
Crystal oscillator 2 output.
Leave open if XTAL2 is not used.
XTAL3_IN E1 I Analog
Crystal oscillator 3 input.
Determines second of two frequency families (chosen from Sonet/SDH, Ethernet or
Ethernet*66/64) available for APLL1. Connect to ground if XTAL3 is not used.
XTAL3_OUT E2 O Analog
Crystal oscillator 3 output.
Leave open if XTAL3 is not used.
XTAL4_IN M14 I Analog
Crystal oscillator 4 input. Connect to ground if XTAL4 is not used.
Determines second of two frequency families (chosen from Sonet/SDH, Ethernet or
Ethernet*66/64) available for APLL2.
XTAL4_OUT M13 O Analog
Crystal oscillator 4 output.
Leave open if XTAL4 is not used.
Lock Indication Signals
DPLL2_LOCK K11 O CMOS
DPLL2 lock indicator.
This pin goes high when DPLL2 is locked.
DPLL1_LOCK J11 O CMOS
DPLL1 lock indicator.
This pin goes high when DPLL1 is locked.
Microprocessor Interface
INT_REQ C13 O CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by
the HZ_EN bit (b1, INTERRUPT_CNFG) and the INT_POL bit (b0, INTER-
RUPT_CNFG).
I2C_SDA K14
I/O
pull-down
CMOS
I2C_SDA: Serial Data Input/Output
This pin is used as the input/output for the I2C serial data.
I2C_AD1 L8
I
pull-up
CMOS
I2C_AD1: Device Address Bit 1
I2C_AD2 and I2C_AD1 pins are the address bus of the microprocessor interface.
I2C_AD2 L9
I
pull-up
CMOS
I2C_AD2: Device Address Bit 2
I2C_AD2 and I2C_AD1 pins are the address bus of the microprocessor interface.
I2C_SCL K13
I
pull-down
CMOS
I2C_SCL: Serial Clock Line
The I2C serial clock is input on this pin.
JTAG (per IEEE 1149.1)
TRST A14
I
pull-down
CMOS
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS A12
I
pull-up
CMOS
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising
edge of TCK.
TCK B10
I
pull-down
CMOS
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising
edge of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefi-
nitely retain their state.
TDI A8
I
pull-up
CMOS
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
Table 1: Pin Description (Continued)
Name Pin No. I/O Type
Description
1
