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82V3911AUG8

P1-P3P4-P6P7-P9P10-P12
IDT82V3911 DATASHEET SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
Pin Assignment 4 July 1, 2013
1 PIN ASSIGNMENT
Figure 2. Pin Assignment (Top View)
IDT
Co
nf
iden
t
ial
1234567891011121314
A
IC10 VDDA XTAL1_IN CAP1
IN_APL L 1_N
EG
NC NC TDI IC7 NC OSCI TMS IC6 TRST
A
B
IC11 VSSA XTAL1_OUT VSSAO
IN_APLL1_P
OS
NC NC
TDO/
DPLL1_
LOS_lNT
VSSAO TCK VSSA VSSA VSSDO VDDDO
B
C
IC4 VDDA NC CAP2
MFRSYNC_2
K_1PPS
FRSYNC_8K_
1PPS
VDDDO VSSDO VDDA VSSA VDDA VDDA INT_REQ NC
C
D
VSSA VSSAO CAP3 VSSA VDDA NC VSSD VDDD IC2 VDDA VSSA VDDA OUT4 OUT5
D
E
XTAL3_IN XTAL3_ OUT VSSA VSSAO VSSA SONET/SDH VSSD VDDD IC1 VSSA VDDA VSSA OUT2 OUT3
E
F
VDDD VSSD VSSAO VSSA VDDA VSSAO VSSD VDDD VSSD VDDD EX_SYNC1 V DDDO OUT1 VSSDO
F
G
VSSD VDDD VSSAO VSSAO VSSAO VSSD VDDD IC3 VDDD VSSD E X_SYNC2 NC NC NC
G
H
VDDAO VSSAO VDDAO VSSAO VSSAO VSSAO VSSD VDDD VSSD VDDD NC NC RST IN3
H
J
OUT6_NEG OUT6_POS VDDAO VSSAO VDDAO VSSAO VDDAO VSSAO VSSA VDDA
DPL L1_
LOCK
NC IN4 IN5
J
K
VSSAO VSSAO VSSAO VDDAO VSSAO VDDAO VSSAO VSSD V DDD VSSAO
DPL L2_
LOCK
IN6 I2C_SCL I2C_SDA
K
L
OUT7_NEG OUT7_POS VDDAO VSSAO VSSAO VSSAO VSSAO I2C_AD1 I2C_ AD2 CAP4 VSSA CAP5 VSSA CAP6
L
M
VDDAO VSSAO VSSAO VSSAO VDDAO VSSAO VDDAO VSSAO VSSAO VSSAO VSSAO NC XTAL4_OUT XTAL4_ IN
M
N
VSSAO OUT 8_POS VSSAO OUT9_POS VSSAO
IN_APL L 2_P
OS
IN1_POS IN2_POS VSSA XTAL2_ OUT VSSA IC9 VSSAO VSSA
N
P
VDDAO O UT8_NEG VSSAO OUT9_NEG V DDAO
IN_APLL 2_N
EG
IN1_NEG IN2_NEG VDDA XTAL2_IN VDDA IC8 IC5 VDDA
P
1234567891011121314
Diff
Outputs
Outputs Inputs Power Ground
Key:
IDT82V3911 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
Pin Description 5 July 1, 2013
2 PIN DESCRIPTION
Table 1: Pin Description
Name Pin No. I/O Type
Description
1
Global Control Signal
OSCI A11 I CMOS
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
SONET/SDH E6
I
pull-down
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2,
INPUT_MODE_CNFG):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST H13
I
pull-up
CMOS
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the
device will still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
EX_SYNC1 F11
I
pull-down
CMOS
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
EX_SYNC2 G11
I
pull-down
CMOS
EX_SYNC2: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
Input Clock
IN1_POS
IN1_NEG
N7
P7
I LVPECL/LVDS
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
A
2kHz, 4kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz or 625 MHz
clock is differentially input on this pair of pins. Whether the clock signal is LVPECL or
LVDS is automatically detected.
Single-ended input for differential input is also supported. Refer to Chapter 7.3.2.5 Sin-
gle-Ended Input for Differential Input.
IN2_POS
IN2_NEG
N8
P8
I LVPECL/LVDS
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
A
2kHz, 4kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz or 312.5 MHz, 622.08 MHz or 625 MHz
clock is differentially input on this pair of pins. Whether the clock signal is LVPECL or
LVDS is automatically detected.
Single-ended input for differential input is also supported. Refer to Chapter 7.3.2.5 Sin-
gle-Ended Input for Differential Input.
IN3 H14
I
pull-down
CMOS
IN3: Input Clock 3
A
2kHz, 4kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IN4 J13
I
pull-down
CMOS
IN4: Input Clock 4
A
2kHz, 4kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IN5 J14
I
pull-down
CMOS
IN5: Input Clock 5
A
2kHz, 4kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IDT82V3911 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET TWO-CHANNEL PLL FOR 10GBE AND 40GBE
Pin Description 6 July 1, 2013
IN6 K12
I
pull-down
CMOS
IN6: Input Clock 6
A 2kHz, 4kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48
MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IN_APLL1_POS
IN_APLL1_NEG
B5
A5
I pull-down
I pull-up/
pull-down
LVPECL/LVDS/
LVHSTL/SSTL/
HCSL
IN_APLL1_POS / IN_APLL1_NEG: Input Clock to APLL1
Direct input clock to APLL1. This pin is used for test. It can be left floating or a 1k
resistor can be tied from IN_APLL1_POS to ground.
IN_APLL2_POS
IN_APLL2_NEG
N6
P6
I pull-down
I pull-up/
pull-down
LVPECL/LVDS/
LVHSTL/SSTL/
HCSL
IN_APLL2_POS / IN_APLL2_NEG: Input Clock APLL2
Direct input clock to APLL2. This pin is used for test. It can be left floating or a 1k
resistor can be tied from IN_APLL1_POS to ground.
Output Frame Synchronization Signal
FRSYN-
C_8K_1PPS
C6 O CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS Frame Pulse is output on this pin.
MFRSYN-
C_2K_1PPS
C5 O CMOS
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
A 2 kHz signal or a 1PPS Frame Pulse is output on this pin.
Output Clock
OUT1
OUT2
OUT3
OUT4
OUT5
F13
E13
E14
D13
D14
OCMOS
OUT1 ~ OUT5: Output Clock 1 ~ 5
A 1 pps, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
4
, N x T1
5
, N x 13.0 MHz
6
, N x 3.84 MHz
7
, 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz,
51.84 MHz, 77.76 MHz, 25MHz, or 125 MHz clock is output on these pins.
OUT6_POS
OUT6_NEG
J2
J1
O LVPECL/LVDS
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based
(25 MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based
(161.1328125 MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on
this pair of pins from APLL1.
OUT7_POS
OUT7_NEG
L2
L1
O LVPECL/LVDS
OUT7_POS / OUT7_NEG: Positive / Negative Output Clock 7
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based
(25 MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based
(161.1328125 MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on
this pair of pins from APLL1.
OUT8_POS
OUT8_NEG
N2
P2
O LVPECL/LVDS
OUT8_POS / OUT8_NEG: Positive / Negative Output Clock 8
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based
(25 MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based
(161.1328125 MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on
this pair of pins from APLL2.
OUT9_POS
OUT9_NEG
N4
P4
O LVPECL/LVDS
OUT9_POS / OUT9_NEG: Positive / Negative Output Clock 9
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based
(25 MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based
(161.1328125 MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on
this pair of pins from APLL2.
Miscellaneous
CAP1, CAP2,
CAP3
A4, C4, D3 O Analog
CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3
Connect a 10uF capacitor in parallel with a low ESR 100nF capacitor between these
pins and VSS1
CAP4, CAP5,
CAP6
L10, L12, L14 O Analog
CAP4, CAP5 and CAP6: Analog Power Filter Capacitor connection 4 to 6
Connect a 10uF capacitor in parallel with a low ESR 100nF capacitor between these
pins and VSS2
Table 1: Pin Description (Continued)
Name Pin No. I/O Type
Description
1
P1-P3P4-P6P7-P9P10-P12

82V3911AUG8

Mfr. #:
Buy 82V3911AUG8
Manufacturer:
IDT
Description:
Clock Generators & Support Products SyncE Two Chan PLL for 10GbE and 40GbE
Lifecycle:
New from this manufacturer.
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