84021 Data Sheet 260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
84021 Rev E 9/23/15 2 ©2015 Integrated Device Technology, Inc
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The 84021 features a fully integrated PLL and therefore requires no
external components for setting the loop bandwidth. A fundamental
crystal is used as the input to the on-chip oscillator. The output of the
oscillator is fed into the phase detector. A 25MHz crystal provides a
25MHz phase detector reference frequency. The VCO of the PLL
operates over a range of 620MHz to 780MHz. The output of the M
divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVCMOS output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the 84021 support two input modes to
program the M divider and N output divider. The two input operational
modes are parallel and serial. Figure 1 shows the timing diagram for
each mode. In parallel mode, the nP_LOAD input is initially LOW.
The data on inputs M0 through M8 and N0 and N1 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial
event occurs. As a result, the M and N bits can be hardwired to set
the M divider and N output divider to a specific default state that will
automatically occur during power-up. The TEST output is LOW when
operating in the parallel input mode. The relationship between the
VCO frequency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 25MHz reference are
defined as 25 M 31. The frequency out is defined as follows:
FOUT = fVCO
= fxtal x M
NN
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
Figure 1. Parallel & Serial Load Operations
T1 T0 TEST Output
00LOW
0 1 S_DATA, Shift Register Input
1 0 Output of M Divider
1 1 CMOS FOUT
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
M0M1M2M3M4M5M6M7M8N0N1*NULLT0T1
S_CLOCK
S_DATA
S_LOAD
S_LOAD
nP_LOAD
M[0:8], N[0:1]
nP_LOAD
*NOTE: The NULL timing slot must be observed.
