84021 Data Sheet 260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
84021 Rev E 9/23/15 14 ©2015 Integrated Device Technology, Inc
Layout Guideline
Figure 3 shows a schematic example of the 84021. In this example,
a series termination is shown. Additional LVCMOS termination
approaches are shown in the LVCMOS Termination Application Note.
In this example, an 18pF parallel resonant crystal is used. The C1 =
22pF and C2 = 22pF are approximate values for frequency accuracy.
The C1 and C2 may be slightly adjusted for optimizing frequency
accuracy.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The 84021 provides separate power
supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Figure 3. 84021 Application Schematic Example
C17
0.1uF
C18
10uF
3.3V
BLM18BB221SN1
Ferrite Bead
1 2
VDDA
C20
10uF
3.3V, 2.5V or 1.8V
BLM18BB221SN2
Ferrite Bead
1 2
C19
0.1uF
C15
0.1u
C16
10u
R7
15 - 24
C14
0.1u
U1
ICS84021
M5
1
M6
2
M7
3
M8
4
N0
5
N1
6
nc
7
GND
8
TEST
9
VDD
10
OE1
11
OE0
12
VDDO
13
Q1
14
Q0
15
GND
16
MR
17
S_CLOCK
18
S_DATA
19
S_LOAD
20
VDDA
21
nXTAL_SEL
22
T_CLK
23
X_OU T
24
M4
32
M3
31
M2
30
M1
29
M0
28
VCO_SEL
27
nP_LOAD
26
X_IN
25
Set Logic
Input to '0'
To Logic
Input
pins
To Logic
Input
pins
RU2
Not Install
C2
22p
RU1
1K
RD2
1K
RD1
Not Install
X1
18pF
R2
43
C11
0.01u
C1
22p
R1
43
Zo = 50 Ohm
Zo = 50 Ohm
VDD
VDD
VDDO
VDD VDD
Set Logic
Input to '1'
Logic Input Pin Examples
